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digital-adder-source-code
- FPGA的Altera Quartus II 利用汇编语言实现加法器数码管的现实程序源代码-The Altera Quartus II FPGA using assembly language to achieve the reality of digital adder source code
VGA-LCD
- 用Altera Quartus II 的VHDL语言来完成LCD的液晶显示汉子功能-The use of Altera Quartus II VHDL language to complete the function of LCD liquid crystal display man
state-machine-code
- 用Altera Quartus II 的VHDL语言完成的状态机控制步进电机的程序员代码-The use of Altera Quartus II VHDL language to complete the state machine code programmer stepper motor control
PWM-waveform
- 用Altera Quartus II 的VHDL语言完成的PWM波形产生的源代码-Altera Quartus II VHDL with the completion of the PWM waveform generation language source code
I2Cread-and-write-the-language
- 用Altera Quartus II 的VHDL语言完成的I2C读写数码管显示源代码-Altera Quartus II VHDL with the completion of the I2C read and write the language digital display source code
Quartus-II
- Altera® Quartus® II 设计软件是用于可编程片上系统 (SOPC) 的最全面的设 计环境。-Altera ® Quartus ® II design software is used for system-on-programmable chip (SOPC) the most comprehensive design environment.
Quartus_Modelsim_setup
- communication between quartus II and modelsim altera
test_sdram
- 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block,
song-play
- 本文作者创新点是基于FPGA完成乐曲演奏电路，在Altera Quartus II 环境下，用VHDL 语言实现电子琴演奏音乐的设计实例，设计者根据VHDL的语法规则，对系统的逻辑行为进行描述，然后通过综合工具进行电路结构的综合、编译、优化，用仿真，可在短时间内设计出高效、稳定、符合设计要求的电路。-This innovation is the author of music to play based on FPGA to complete the circuit, the Altera Qu
quartus
- Quartus II使用教程，Quartus II是Altera公司推出的CPLD/FPGA开发工具，Quartus II提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性-Quartus II using the tutorial, Quartus II Altera Corporation launched CPLD/FPGA development tool, Quartus II development kit provides a fully integrated
Altera Qsys Design Tutorial
- The Qsys System Design Tutorial (PDF) provides step-by-step instructions to create and verify a design with the Qsys system integration tool in the Quartus® II software. This design example includes the system components to design a memory tester sys
DE2_SD_Card_Audio(quartus-9.0)
- 本代码为Altera DE2开发板例程源码（EP2C35F672C6)，quartus II 9.0以上版本均可编译（随板光盘为quartus II 7.2版在9.0以上版本上编译会报错）。本工程实现SD的音频播放器，即通过FPGA控制SD卡，读取SD的音频文件，通过WM8731进行播放。-In this demonstration we show how to implement an SD Card Music Player on the DE2 board, in which th
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA
key0
- Keys Altera Quartus II 9.0 Altera MAX II While key is on then diod is on
fm_verilog
- A simple frequency division program for altera Quartus II 13.0 (32-bit) Web Edition .it is runing at Altera FPGA
Quartus-7.2-32-Bit-Crack-Bundle
- License generators and license.dat to quartus II ALtera
master_sc
- altera quartus II version 15.0 master
master_bla
- master bla altera quartus II version 15
Crack_QII_14.0_Windows
- altera quartus II crack 14
lab_5
- Introduction to learn laboratry with altera quartus II 9.1