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exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复! 2.运行时请注意完整路径: D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题? 3.1 MODELSIM中w完信号后,run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
QuatersCrack
- 可以用于破解Quartus II 9.0,9.0SP2,9.1。 内部已经有说明文档。-Cracker for Quartus II 9.0,9.0SP2,9.1. Notice the readme file in it.
chengfaqi
- verilog语言编写的一个乘法器程序,是16位相乘!已通过仿真,用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
vga
- verilog语言编写的一个vga程序,是vga显示程序,用Quartus II 9.1 编写-a vga verilog language program is a vga display program, the Quartus II 9.1 to write
lcd
- verilog语言编写的一个lcd控制程序,是lcd显示程序,用Quartus II 9.1 编写-verilog language lcd control procedures, lcd display program written using the Quartus II 9.1
Code_NCO.zip
- 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
COUNTER
- a counter upward and donward until a certain number, designed on the quartus 2 web edition 9.1 simple code
abc
- 在Quartus II 9.1下开发FPGA/CPLD程序的使用教程操作笔记-Quartus II 9.1 developed under the operation of the FPGA/CPLD program using the tutorial notes
q_74ls138
- 在quartus II 9.1上用verilog原理图形式实现的74ls138功能的38译码器-38 of 74ls138 features achieve verilog schematic form in quartus II 9.1 decoder
FPGA_Test_Cap
- 波形采集示例源码,在Quartus II 9.1 SP2环境下编译通过。-Waveform acquisition sample source code, compiled by the Quartus II 9.1 SP2 environment.
sine-function-generator-design
- 一个正弦发生器的设计,应用于EP2C35F672C6开发板,仿真环境为Quartus II 9.1 -A sine generator design, based on EP2C35F672C6 board. Simulated in Quartus II 9.1
DE2_SD_Card_Audio
- 使用Quartus Ⅱ与 NIOS Ⅱ IDE。 功能要求:(可实现某几项或全部) 1. 支持SD卡文件读取; 2. 支持WAV或MP3或其他格式音频,如为压缩格式则需解压缩; 3. 歌曲名称LCD显示; 4. 支持“播放/暂停”控制功能; 5. 支持“前一首”功能; 6. 支持“下一首”功能; 7. 支持LED灯显示音量功能; 8. 支持复位功能; 9. 支持硬启动,FPGA码流文件和软件二进制文件写入ROM,从ROM启动; 10. 支持总歌曲数和第
eluosi_game
- 使用Quartus II 9.1完成俄罗斯方块游戏,只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单,使用的是VHDL和Verilog语言-Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use
fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现,在任意开发板上都能实现。操作简单,使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
lab_5
- Introduction to learn laboratry with altera quartus II 9.1
quartus ii 9.0 (1)
- 按钮您就能叫你家那叫奶奶看见了就能理解你(buttonjnknjknjnjnkjn)