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Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
gsmch
- gsm的卷积码编码和viterbi译码的源码-gsm convolution encoder and Viterbi decoding FOSS
viterbidecoder
- 提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
TELECOM2
- This file contains program files associated with the paper titled "US Digital Cellular Error-Correction Coding Algorithm Implementation on the TMS320C5x", Telecom Applications With The TMS320C5x DSPs, Application Book, 1994, SPRA033. This file c
VB_decode
- Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
verterbicode
- 使用dsp编程，实现信道编码中卷积编码，并使用维特比对编码进行译码。-Use dsp programming, channel coding convolutional coding and Viterbi decoding on the encoding.
convolutional_code
- 卷积码编码,经过模拟的有噪信道,viterbi译码,汇编实现-Convolutional coding, through the simulation of noisy channel, viterbi decoding, compiling achieve
codec54x
- 卷积编码和维特比译码在C54上的实现，该程序采用C和汇编混合编程的方式。-Convolutional coding and Viterbi decoding on the C54 implementation, the program mixed with C and assembler programming approach.
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Viterbi_check
- It is a verilog code for viterbi decoding with trellis diagram
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
viterbi
- 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
DSP-Viterbi
- 应用DSP的viterbi译码及实现，含例程，希望对大家有用-Application of the viterbi decoding and implementation of DSP, including routine, we hope to be useful
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Design-Space-Exploration-of-Hard-Decision-Viterbi
- Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation