搜索资源列表
jtag0
- 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
codestream
- 设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
pcm
- 该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
Evita_VHDL
- VHDL 的非常好用易懂的教学软件。大家试试看。-VHDL very handy and easy to teaching software. We try.
wom_kg
- 系统时钟的VHDL电路，适合有一定经验的编程人员，希望能对你们有帮助。-VHDL system clock circuit suitable for a certain programming experience, you want to help.
16_risc_cpu
- 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
cordic_beh
- 这是实现cordic算法的一些源程序，各文件的说明可以参见文件内部注释。 -This is the algorithm Coordinate rotation digital source, the documents of the internal documents can be found in the Notes.
fulladd
- 用于实现两个数相加的vhdl代码，在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler
Exp6-VGA
- 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
66vhdl_src
- 66个vhdl的常用源代码，包括有双向口、状态机等，自解压后看vhdl_example.html列表说明.exe-66 vhdl common source code, including the two-mouth state machine, Since unpacked see vhdl_example.html tabulated. exe
ModelSim6c_SE_Cracker
- crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL / Verilog simulator for CAD F PGA, board and IC design.
count60_dec_bcd_led
- 是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
WinFilter08
- WinFilter is a software tool provided as freeware to design digital filter.-WinFilter is a software tool provided as fr eeware to design digital filter.
sourceIIR6
- IIR 六阶数字滤波器的 VHD L 描述-six-IIR Digital Filter Volume L Descr iption
E016_X-HDL3.2.52
- VHDL和Verilog代码互转工具,对EDA工程人员会有很大的帮助.-VHDL and Verilog code referrals tools, EDA staff to be very helpful.
xst3_video
- 基于XILINX的XC3系列FPGA的VGA控制器的VHDL源程序。-based on the XC3 XILINX FPGA series VGA controller VHDL source.
vhdltoverilog
- vhdl to verilog语言的编程设计，很有参考价值。-vhdl to verilog programming language design, great reference value.
quartusII7.1crack
- quartus_II_7.1的license破解工具，很好用
DspBuilder6.0_License
- DspBulider6.0的license破解