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juanjima
- simulink实现卷积码的编译码功能，以及误码率分析.-BER simulink
69491753mentos_fs
- GSM信道中卷积码编码以及相应的维特比译码的全部Matlab代码-GSM channelcross code vitibi decode all matlab program
DSP_based_power_line_modem
- 基于DSP的电力线调制解调器及其驱动程序的研究，包括OFDM调制技术、卷积码、交织编码和Turbo码编码技术、同步、访问控制方式等关键技术。研究生毕业论文，花银子买的，现在无私贡献出来咯！不可多得，叙述非常详尽，仅供参考！-DSP-based power line modem and its drivers, including studies on OFDM modulation, convolutional codes, interleaving coding and Turbo codin
W607
- 本文首先介绍了两种协作方式与OFDM框架，并结合OFDM技术进行了系统仿真，对比分析了OFDM系统与CRC编码OFDM系统与卷积码编码OFDM系统仿真性能。-two methods to realize cooperative diversity in OFDM systems are proposed simulations using OFDM techniques are performed and the performance of the CRC coding OFDM syst
dsp
- 卷积码和维特比的编码及译码原理，MATLAB的仿真图。-Convolutional code and Viterbi encoding and decoding principle, MATLAB simulation of Fig.
123
- 基于DSP的信道编译码以及卷积码和维特比译码的代码-Based on DSP channel encoding and decoding convolutional code and Viterbi decoding code
iterbi
- 约束长度为9的卷积码解码，viterbi解码，加上高斯白噪声了-Constraint length 9 convolutional code decoding, viterbi decoding, white Gaussian noise with a
CPP
- 用C++编写了卷积码的译码，运行过了没问题-Prepared with C++ convolutional code decoding, run over no problem
rs_code
- 本文在介绍卷积码原理和描述方式的基础上以1/2卷积码为例重点详细阐述了基于Verilog HDL 的卷积码的编器的设计-This paper introduced the convolution code on the principles and methods described in 1/2 convolutional code as an example focuses elaborated convolution based on Verilog HDL code compiled
punctured-convolutional-codes
- 本文是一篇优秀硕士毕业论文提出一种基于校验矩阵的删除卷积码的识别方法。 - In this paper, a code rate recognition method for punctured convolutional code has been proposed based on parity check matrix.
covolutional
- 1/2码率，64状态，卷积编码，采用格型编码，QPSK调制-Rate 1/2, 64 state convolutional coding using trellis coding, QPSK modulation
a-convolution-of-the-code-decoder
- matlab卷积码编译码译码器设计仿真，做毕业论文很有参考价值-matlab convolutional code decoder codec design simulation, doing thesis of great reference value
802.11b_bcc-and-viterbi-encoder
- 讲解802.11b的卷积码和viterbi译码的FPGA设计实现方式和方法-intruduce the fpga realization of 802.11b protol bcc and viterbi decoder
verilog-2-1-4
- 卷积码（2,1,4）编解码的FPGA实现-Convolution code (2,1,4) decoding the FPGA implementation