文件名称:clk_div3
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- 上传时间:2012-11-16
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文件大小:274.95kb
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介绍说明--下载内容来自于网络,使用问题请自行百度
在fpga中对于pll无法完成的分频,可采用计数方式,本例用状态机实现对时钟的奇数分频。-Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_div3/clk_div3.asm.rpt
clk_div3/clk_div3.cdf
clk_div3/clk_div3.done
clk_div3/clk_div3.eda.rpt
clk_div3/clk_div3.fit.rpt
clk_div3/clk_div3.fit.smsg
clk_div3/clk_div3.fit.summary
clk_div3/clk_div3.flow.rpt
clk_div3/clk_div3.map.rpt
clk_div3/clk_div3.map.summary
clk_div3/clk_div3.pin
clk_div3/clk_div3.pof
clk_div3/clk_div3.qpf
clk_div3/clk_div3.qsf
clk_div3/clk_div3.qws
clk_div3/clk_div3.sof
clk_div3/clk_div3.sta.rpt
clk_div3/clk_div3.sta.summary
clk_div3/clk_div3.v
clk_div3/clk_div3.v.bak
clk_div3/clk_div3_nativelink_simulation.rpt
clk_div3/db/clk_div3.(0).cnf.cdb
clk_div3/db/clk_div3.(0).cnf.hdb
clk_div3/db/clk_div3.asm.qmsg
clk_div3/db/clk_div3.cbx.xml
clk_div3/db/clk_div3.cmp.ecobp
clk_div3/db/clk_div3.cmp.rdb
clk_div3/db/clk_div3.cmp0.ddb
clk_div3/db/clk_div3.cmp1.ddb
clk_div3/db/clk_div3.cmp2.ddb
clk_div3/db/clk_div3.cmp_bb.cdb
clk_div3/db/clk_div3.cmp_bb.hdb
clk_div3/db/clk_div3.cmp_bb.logdb
clk_div3/db/clk_div3.cmp_bb.rcf
clk_div3/db/clk_div3.dbp
clk_div3/db/clk_div3.db_info
clk_div3/db/clk_div3.eco.cdb
clk_div3/db/clk_div3.eda.qmsg
clk_div3/db/clk_div3.fit.qmsg
clk_div3/db/clk_div3.hier_info
clk_div3/db/clk_div3.hif
clk_div3/db/clk_div3.map.bpm
clk_div3/db/clk_div3.map.cdb
clk_div3/db/clk_div3.map.ecobp
clk_div3/db/clk_div3.map.hdb
clk_div3/db/clk_div3.map.logdb
clk_div3/db/clk_div3.map.qmsg
clk_div3/db/clk_div3.map_bb.cdb
clk_div3/db/clk_div3.map_bb.hdb
clk_div3/db/clk_div3.map_bb.logdb
clk_div3/db/clk_div3.pre_map.cdb
clk_div3/db/clk_div3.pre_map.hdb
clk_div3/db/clk_div3.psp
clk_div3/db/clk_div3.pss
clk_div3/db/clk_div3.rtlv.hdb
clk_div3/db/clk_div3.rtlv_sg.cdb
clk_div3/db/clk_div3.rtlv_sg_swap.cdb
clk_div3/db/clk_div3.sgdiff.cdb
clk_div3/db/clk_div3.sgdiff.hdb
clk_div3/db/clk_div3.sld_design_entry.sci
clk_div3/db/clk_div3.sld_design_entry_dsc.sci
clk_div3/db/clk_div3.sta.qmsg
clk_div3/db/clk_div3.sta.rdb
clk_div3/db/clk_div3.syn_hier_info
clk_div3/db/clk_div3.tis_db_list.ddb
clk_div3/db/logic_util_heursitic.dat
clk_div3/db/prev_cmp_clk_div3.asm.qmsg
clk_div3/db/prev_cmp_clk_div3.eda.qmsg
clk_div3/db/prev_cmp_clk_div3.fit.qmsg
clk_div3/db/prev_cmp_clk_div3.map.qmsg
clk_div3/db/prev_cmp_clk_div3.qmsg
clk_div3/db/prev_cmp_clk_div3.sta.qmsg
clk_div3/incremental_db/compiled_partitions/clk_div3.db_info
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.cdb
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.dpi
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.hdb
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.kpt
clk_div3/incremental_db/README
clk_div3/simulation/modelsim/clk_div3.vo
clk_div3/simulation/modelsim/clk_div3.vt
clk_div3/simulation/modelsim/clk_div3.vt.bak
clk_div3/simulation/modelsim/clk_div3_fast.vo
clk_div3/simulation/modelsim/clk_div3_modelsim.xrf
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do.bak
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do.bak1
clk_div3/simulation/modelsim/clk_div3_v.sdo
clk_div3/simulation/modelsim/clk_div3_v_fast.sdo
clk_div3/simulation/modelsim/modelsim.ini
clk_div3/simulation/modelsim/msim_transcript
clk_div3/simulation/modelsim/rtl_work/clk_div3/verilog.psm
clk_div3/simulation/modelsim/rtl_work/clk_div3/_primary.dat
clk_div3/simulation/modelsim/rtl_work/clk_div3/_primary.vhd
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/verilog.psm
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/_primary.dat
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/_primary.vhd
clk_div3/simulation/modelsim/rtl_work/_info
clk_div3/simulation/modelsim/vsim.wlf
clk_div3/simulation/modelsim/rtl_work/clk_div3
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst
clk_div3/simulation/modelsim/rtl_work
clk_div3/incremental_db/compiled_partitions
clk_div3/simulation/modelsim
clk_div3/db
clk_div3/incremental_db
clk_div3/simulation
clk_div3
clk_div3/clk_div3.cdf
clk_div3/clk_div3.done
clk_div3/clk_div3.eda.rpt
clk_div3/clk_div3.fit.rpt
clk_div3/clk_div3.fit.smsg
clk_div3/clk_div3.fit.summary
clk_div3/clk_div3.flow.rpt
clk_div3/clk_div3.map.rpt
clk_div3/clk_div3.map.summary
clk_div3/clk_div3.pin
clk_div3/clk_div3.pof
clk_div3/clk_div3.qpf
clk_div3/clk_div3.qsf
clk_div3/clk_div3.qws
clk_div3/clk_div3.sof
clk_div3/clk_div3.sta.rpt
clk_div3/clk_div3.sta.summary
clk_div3/clk_div3.v
clk_div3/clk_div3.v.bak
clk_div3/clk_div3_nativelink_simulation.rpt
clk_div3/db/clk_div3.(0).cnf.cdb
clk_div3/db/clk_div3.(0).cnf.hdb
clk_div3/db/clk_div3.asm.qmsg
clk_div3/db/clk_div3.cbx.xml
clk_div3/db/clk_div3.cmp.ecobp
clk_div3/db/clk_div3.cmp.rdb
clk_div3/db/clk_div3.cmp0.ddb
clk_div3/db/clk_div3.cmp1.ddb
clk_div3/db/clk_div3.cmp2.ddb
clk_div3/db/clk_div3.cmp_bb.cdb
clk_div3/db/clk_div3.cmp_bb.hdb
clk_div3/db/clk_div3.cmp_bb.logdb
clk_div3/db/clk_div3.cmp_bb.rcf
clk_div3/db/clk_div3.dbp
clk_div3/db/clk_div3.db_info
clk_div3/db/clk_div3.eco.cdb
clk_div3/db/clk_div3.eda.qmsg
clk_div3/db/clk_div3.fit.qmsg
clk_div3/db/clk_div3.hier_info
clk_div3/db/clk_div3.hif
clk_div3/db/clk_div3.map.bpm
clk_div3/db/clk_div3.map.cdb
clk_div3/db/clk_div3.map.ecobp
clk_div3/db/clk_div3.map.hdb
clk_div3/db/clk_div3.map.logdb
clk_div3/db/clk_div3.map.qmsg
clk_div3/db/clk_div3.map_bb.cdb
clk_div3/db/clk_div3.map_bb.hdb
clk_div3/db/clk_div3.map_bb.logdb
clk_div3/db/clk_div3.pre_map.cdb
clk_div3/db/clk_div3.pre_map.hdb
clk_div3/db/clk_div3.psp
clk_div3/db/clk_div3.pss
clk_div3/db/clk_div3.rtlv.hdb
clk_div3/db/clk_div3.rtlv_sg.cdb
clk_div3/db/clk_div3.rtlv_sg_swap.cdb
clk_div3/db/clk_div3.sgdiff.cdb
clk_div3/db/clk_div3.sgdiff.hdb
clk_div3/db/clk_div3.sld_design_entry.sci
clk_div3/db/clk_div3.sld_design_entry_dsc.sci
clk_div3/db/clk_div3.sta.qmsg
clk_div3/db/clk_div3.sta.rdb
clk_div3/db/clk_div3.syn_hier_info
clk_div3/db/clk_div3.tis_db_list.ddb
clk_div3/db/logic_util_heursitic.dat
clk_div3/db/prev_cmp_clk_div3.asm.qmsg
clk_div3/db/prev_cmp_clk_div3.eda.qmsg
clk_div3/db/prev_cmp_clk_div3.fit.qmsg
clk_div3/db/prev_cmp_clk_div3.map.qmsg
clk_div3/db/prev_cmp_clk_div3.qmsg
clk_div3/db/prev_cmp_clk_div3.sta.qmsg
clk_div3/incremental_db/compiled_partitions/clk_div3.db_info
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.cdb
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.dpi
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.hdb
clk_div3/incremental_db/compiled_partitions/clk_div3.root_partition.map.kpt
clk_div3/incremental_db/README
clk_div3/simulation/modelsim/clk_div3.vo
clk_div3/simulation/modelsim/clk_div3.vt
clk_div3/simulation/modelsim/clk_div3.vt.bak
clk_div3/simulation/modelsim/clk_div3_fast.vo
clk_div3/simulation/modelsim/clk_div3_modelsim.xrf
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do.bak
clk_div3/simulation/modelsim/clk_div3_run_msim_rtl_verilog.do.bak1
clk_div3/simulation/modelsim/clk_div3_v.sdo
clk_div3/simulation/modelsim/clk_div3_v_fast.sdo
clk_div3/simulation/modelsim/modelsim.ini
clk_div3/simulation/modelsim/msim_transcript
clk_div3/simulation/modelsim/rtl_work/clk_div3/verilog.psm
clk_div3/simulation/modelsim/rtl_work/clk_div3/_primary.dat
clk_div3/simulation/modelsim/rtl_work/clk_div3/_primary.vhd
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/verilog.psm
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/_primary.dat
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst/_primary.vhd
clk_div3/simulation/modelsim/rtl_work/_info
clk_div3/simulation/modelsim/vsim.wlf
clk_div3/simulation/modelsim/rtl_work/clk_div3
clk_div3/simulation/modelsim/rtl_work/clk_div3_vlg_tst
clk_div3/simulation/modelsim/rtl_work
clk_div3/incremental_db/compiled_partitions
clk_div3/simulation/modelsim
clk_div3/db
clk_div3/incremental_db
clk_div3/simulation
clk_div3
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