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文件名称:Myszz

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    767.85kb
  • 已下载：
    0次
  • 提 供 者：
    吕****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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基于EDA的用VerlogHDL编写的多功能数字闹钟-EDA' s written by VerlogHDL based multifunction digital alarm clock
相关搜索： vhdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

My szz—Verilog/clk_10hz(1).cnf
My szz—Verilog/clk_10hz(10).cnf
My szz—Verilog/clk_10hz(2).cnf
My szz—Verilog/clk_10hz(3).cnf
My szz—Verilog/clk_10hz(4).cnf
My szz—Verilog/clk_10hz(5).cnf
My szz—Verilog/clk_10hz(6).cnf
My szz—Verilog/clk_10hz(7).cnf
My szz—Verilog/clk_10hz(8).cnf
My szz—Verilog/clk_10hz(9).cnf
My szz—Verilog/clk_10hz.acf
My szz—Verilog/clk_10hz.cnf
My szz—Verilog/clk_10hz.fit
My szz—Verilog/clk_10hz.hex
My szz—Verilog/clk_10hz.hif
My szz—Verilog/clk_10Hz.inc
My szz—Verilog/clk_10hz.mmf
My szz—Verilog/clk_10hz.ndb
My szz—Verilog/clk_10hz.pin
My szz—Verilog/clk_10hz.pof
My szz—Verilog/clk_10hz.rpt
My szz—Verilog/clk_10hz.scf
My szz—Verilog/clk_10hz.snf
My szz—Verilog/clk_10hz.sof
My szz—Verilog/clk_10Hz.sym
My szz—Verilog/clk_10hz.ttf
My szz—Verilog/clk_10HZ.v
My szz—Verilog/clk_div(1).cnf
My szz—Verilog/clk_div(2).cnf
My szz—Verilog/clk_div(3).cnf
My szz—Verilog/clk_div(4).cnf
My szz—Verilog/clk_div.acf
My szz—Verilog/clk_div.cnf
My szz—Verilog/clk_div.fit
My szz—Verilog/clk_div.hex
My szz—Verilog/clk_div.hif
My szz—Verilog/clk_div.mmf
My szz—Verilog/clk_div.ndb
My szz—Verilog/clk_div.pin
My szz—Verilog/clk_div.pof
My szz—Verilog/clk_div.rpt
My szz—Verilog/clk_div.snf
My szz—Verilog/clk_div.sof
My szz—Verilog/clk_div.sym
My szz—Verilog/clk_div.ttf
My szz—Verilog/clk_div.v
My szz—Verilog/clk_div_s(1).cnf
My szz—Verilog/clk_div_s(10).cnf
My szz—Verilog/clk_div_s(2).cnf
My szz—Verilog/clk_div_s(3).cnf
My szz—Verilog/clk_div_s(4).cnf
My szz—Verilog/clk_div_s(5).cnf
My szz—Verilog/clk_div_s(6).cnf
My szz—Verilog/clk_div_s(7).cnf
My szz—Verilog/clk_div_s(8).cnf
My szz—Verilog/clk_div_s(9).cnf
My szz—Verilog/clk_div_s.acf
My szz—Verilog/clk_div_s.cnf
My szz—Verilog/clk_div_s.fit
My szz—Verilog/clk_div_s.hex
My szz—Verilog/clk_div_s.hif
My szz—Verilog/clk_div_s.mmf
My szz—Verilog/clk_div_s.ndb
My szz—Verilog/clk_div_s.pin
My szz—Verilog/clk_div_s.pof
My szz—Verilog/clk_div_s.rpt
My szz—Verilog/clk_div_s.snf
My szz—Verilog/clk_div_s.sof
My szz—Verilog/clk_div_s.sym
My szz—Verilog/clk_div_s.ttf
My szz—Verilog/clk_div_s.v
My szz—Verilog/counter23(1).cnf
My szz—Verilog/counter23(2).cnf
My szz—Verilog/counter23(3).cnf
My szz—Verilog/counter23(4).cnf
My szz—Verilog/counter23(5).cnf
My szz—Verilog/counter23(6).cnf
My szz—Verilog/counter23(7).cnf
My szz—Verilog/counter23.acf
My szz—Verilog/counter23.cnf
My szz—Verilog/counter23.fit
My szz—Verilog/counter23.hex
My szz—Verilog/counter23.hif
My szz—Verilog/counter23.inc
My szz—Verilog/counter23.mmf
My szz—Verilog/counter23.ndb
My szz—Verilog/counter23.pin
My szz—Verilog/counter23.pof
My szz—Verilog/counter23.rpt
My szz—Verilog/counter23.scf
My szz—Verilog/counter23.snf
My szz—Verilog/counter23.sof
My szz—Verilog/counter23.sym
My szz—Verilog/counter23.ttf
My szz—Verilog/counter23.v
My szz—Verilog/counter59.acf
My szz—Verilog/counter59.hif
My szz—Verilog/counter59_fen(1).cnf
My szz—Verilog/counter59_fen(2).cnf
My szz—Verilog/counter59_fen(3).cnf
My szz—Verilog/counter59_fen(4).cnf
My szz—Verilog/counter59_fen(5).cnf
My szz—Verilog/counter59_fen(6).cnf
My szz—Verilog/counter59_fen.acf
My szz—Verilog/counter59_fen.cnf
My szz—Verilog/counter59_fen.fit
My szz—Verilog/counter59_fen.hex
My szz—Verilog/counter59_fen.hif
My szz—Verilog/counter59_fen.mmf
My szz—Verilog/counter59_fen.ndb
My szz—Verilog/counter59_fen.pin
My szz—Verilog/counter59_fen.pof
My szz—Verilog/counter59_fen.rpt
My szz—Verilog/counter59_fen.scf
My szz—Verilog/counter59_fen.snf
My szz—Verilog/counter59_fen.sof
My szz—Verilog/counter59_fen.sym
My szz—Verilog/counter59_fen.ttf
My szz—Verilog/counter59_fen.v
My szz—Verilog/counter59_miao(1).cnf
My szz—Verilog/counter59_miao(2).cnf
My szz—Verilog/counter59_miao(3).cnf
My szz—Verilog/counter59_miao(4).cnf
My szz—Verilog/counter59_miao.acf
My szz—Verilog/counter59_miao.cnf
My szz—Verilog/counter59_miao.fit
My szz—Verilog/counter59_miao.hex
My szz—Verilog/counter59_miao.hif
My szz—Verilog/counter59_miao.mmf
My szz—Verilog/counter59_miao.ndb
My szz—Verilog/counter59_miao.pin
My szz—Verilog/counter59_miao.pof
My szz—Verilog/counter59_miao.rpt
My szz—Verilog/counter59_miao.snf
My szz—Verilog/counter59_miao.sof
My szz—Verilog/counter59_miao.sym
My szz—Verilog/counter59_miao.ttf
My szz—Verilog/counter59_miao.v
My szz—Verilog/fengminqi.acf
My szz—Verilog/fengminqi.cnf
My szz—Verilog/fengminqi.fit
My szz—Verilog/fengminqi.hex
My szz—Verilog/fengminqi.hif
My szz—Verilog/fengminqi.inc
My szz—Verilog/fengminqi.mmf
My szz—Verilog/fengminqi.ndb
My szz—Verilog/fengminqi.pin
My szz—Verilog/fengminqi.pof
My szz—Verilog/fengminqi.rpt
My szz—Verilog/fengminqi.snf
My szz—Verilog/fengminqi.sof
My szz—Verilog/fengminqi.sym
My szz—Verilog/fengminqi.ttf
My szz—Verilog/fengminqi.v
My szz—Verilog/in_de.acf
My szz—Verilog/in_de.hif
My szz—Verilog/in_de.v
My szz—Verilog/key_m(1).cnf
My szz—Verilog/key_m(2).cnf
My szz—Verilog/key_m(3).cnf
My szz—Verilog/key_m(4).cnf
My szz—Verilog/key_m(5).cnf
My szz—Verilog/key_m(6).cnf
My szz—Verilog/key_m(7).cnf
My szz—Verilog/key_m.acf
My szz—Verilog/key_m.cnf
My szz—Verilog/key_m.fit
My szz—Verilog/key_m.hex
My szz—Verilog/key_m.hif
My szz—Verilog/key_m.mmf
My szz

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