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文件名称:ADC

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    474.91kb
  • 已下载：
    0次
  • 提 供 者：
    zho***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

actel fpga kit 使用的模数转换程序-actel fpga kit used in analog to digital conversion process
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ADC实验/Source Files/ADC.V
ADC实验/Project/ADC/ADC.prj
ADC实验/Project/ADC/assert.log
ADC实验/Project/ADC/viewdraw/viewdraw.ini
ADC实验/Project/ADC/viewdraw/vf/project.lst
ADC实验/Project/ADC/synthesis/ADC.areasrr
ADC实验/Project/ADC/synthesis/ADC.edn
ADC实验/Project/ADC/synthesis/ADC.fse
ADC实验/Project/ADC/synthesis/ADC.htm
ADC实验/Project/ADC/synthesis/ADC.map
ADC实验/Project/ADC/synthesis/ADC.sap
ADC实验/Project/ADC/synthesis/ADC.sdf
ADC实验/Project/ADC/synthesis/ADC.so
ADC实验/Project/ADC/synthesis/ADC.srd
ADC实验/Project/ADC/synthesis/ADC.srm
ADC实验/Project/ADC/synthesis/ADC.srr
ADC实验/Project/ADC/synthesis/ADC.srs
ADC实验/Project/ADC/synthesis/ADC.tlg
ADC实验/Project/ADC/synthesis/ADC_drc.rpt
ADC实验/Project/ADC/synthesis/ADC_sdc.sdc
ADC实验/Project/ADC/synthesis/ADC_syn.prj
ADC实验/Project/ADC/synthesis/MY_ADC.areasrr
ADC实验/Project/ADC/synthesis/MY_ADC.edn
ADC实验/Project/ADC/synthesis/MY_ADC.fse
ADC实验/Project/ADC/synthesis/MY_ADC.htm
ADC实验/Project/ADC/synthesis/MY_ADC.map
ADC实验/Project/ADC/synthesis/MY_ADC.sap
ADC实验/Project/ADC/synthesis/MY_ADC.sdf
ADC实验/Project/ADC/synthesis/MY_ADC.so
ADC实验/Project/ADC/synthesis/MY_ADC.srd
ADC实验/Project/ADC/synthesis/MY_ADC.srm
ADC实验/Project/ADC/synthesis/MY_ADC.srr
ADC实验/Project/ADC/synthesis/MY_ADC.srs
ADC实验/Project/ADC/synthesis/MY_ADC.tlg
ADC实验/Project/ADC/synthesis/MY_ADC_drc.rpt
ADC实验/Project/ADC/synthesis/MY_ADC_sdc.sdc
ADC实验/Project/ADC/synthesis/MY_ADC_syn.prj
ADC实验/Project/ADC/synthesis/run_options.txt
ADC实验/Project/ADC/synthesis/stdout.log
ADC实验/Project/ADC/synthesis/syntmp/ADC.msg
ADC实验/Project/ADC/synthesis/syntmp/ADC.plg
ADC实验/Project/ADC/synthesis/syntmp/ADC_flink.htm
ADC实验/Project/ADC/synthesis/syntmp/ADC_srr.htm
ADC实验/Project/ADC/synthesis/syntmp/ADC_toc.htm
ADC实验/Project/ADC/synthesis/syntmp/MY_ADC.msg
ADC实验/Project/ADC/synthesis/syntmp/MY_ADC.plg
ADC实验/Project/ADC/synthesis/syntmp/MY_ADC_flink.htm
ADC实验/Project/ADC/synthesis/syntmp/MY_ADC_srr.htm
ADC实验/Project/ADC/synthesis/syntmp/MY_ADC_toc.htm
ADC实验/Project/ADC/synthesis/syntmp/sap.log
ADC实验/Project/ADC/synthesis/backup/ADC.srr
ADC实验/Project/ADC/smartgen/MY_ADC_work.ixf
ADC实验/Project/ADC/smartgen/pllclk_work.ixf
ADC实验/Project/ADC/smartgen/smartgen.aws
ADC实验/Project/ADC/smartgen/pllclk/pllclk.cxf
ADC实验/Project/ADC/smartgen/pllclk/pllclk.gen
ADC实验/Project/ADC/smartgen/pllclk/pllclk.log
ADC实验/Project/ADC/smartgen/pllclk/pllclk.v
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.cfg
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.cxf
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.gen
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.log
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.ncf
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC.v
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC_acm.mem
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC_acm_ram.hex
ADC实验/Project/ADC/smartgen/MY_ADC/MY_ADC_acm_ram_R0C0.mem
ADC实验/Project/ADC/simulation/MY_ADC_acm_ram_R0C0.mem
ADC实验/Project/ADC/simulation/modelsim.ini
ADC实验/Project/ADC/simulation/modelsim.ini.sav
ADC实验/Project/ADC/hdl/ADC.V
ADC实验/Project/ADC/hdl/hdlsynchk.tcl
ADC实验/Project/ADC/designer/impl1/ADC.adb
ADC实验/Project/ADC/designer/impl1/ADC.ide_des
ADC实验/Project/ADC/designer/impl1/ADC.lok
ADC实验/Project/ADC/designer/impl1/ADC.pdb
ADC实验/Project/ADC/designer/impl1/ADC.pdb.depends
ADC实验/Project/ADC/designer/impl1/ADC.stp
ADC实验/Project/ADC/designer/impl1/ADC.tcl
ADC实验/Project/ADC/designer/impl1/MY_ADC.tcl
ADC实验/Project/ADC/designer/impl1/ada02508-1.tmp
ADC实验/Project/ADC/designer/impl1/designer.log
ADC实验/Project/ADC/designer/impl1/designer_genhdl.log
ADC实验/Project/ADC/designer/impl1/ADC_fp/$$FlashPro_FPBBALTLPT1.L$$
ADC实验/Project/ADC/designer/impl1/ADC_fp/ADC.log
ADC实验/Project/ADC/designer/impl1/ADC_fp/ADC.pro
ADC实验/Project/ADC/designer/impl1/ADC_fp/projectData/ADC.pdb
ADC实验/Project/ADC/designer/impl1/ADC.dtf/verify.log
ADC实验/Project/ADC/designer/impl1/ADC_fp/projectData
ADC实验/Project/ADC/designer/impl1/simulation
ADC实验/Project/ADC/designer/impl1/ADC_fp
ADC实验/Project/ADC/designer/impl1/ADC.dtf
ADC实验/Project/ADC/viewdraw/wir
ADC实验/Project/ADC/viewdraw/vf
ADC实验/Project/ADC/viewdraw/sym
ADC实验/Project/ADC/viewdraw/sch
ADC实验/Project/ADC/synthesis/syntmp
ADC实验/Project/ADC/synthesis/backup
ADC实验/Project/ADC/smartgen/pllclk
ADC实验/Project/ADC/smartgen/common
ADC实验/Project/ADC/smartgen/MY_ADC
ADC实验/Project/ADC/designer/impl1
ADC实验/Project/ADC/viewdraw
ADC实验/Project/ADC/synthesis
ADC实验/Project/ADC/stimulus
ADC实验/Project/ADC/smartgen
ADC实验/Project/ADC/simulation
ADC实验/Project/ADC/phy_synthesis
ADC实验/Project/ADC/hdl
ADC实验/Project/ADC/designer
ADC实验/Project/ADC/coreconsole
ADC实验/Project/ADC/constraint
ADC实验/Project/ADC/component
ADC实验/Project/ADC
ADC实验/Source Files
ADC实验/Project
ADC实验

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