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文件名称:simpleRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    640.25kb
  • 已下载：
    0次
  • 提 供 者：
    j*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用几种不同的方法设计FPFA片上存储器-Using several different methods of design FPFA-chip memory
(系统自动生成,下载前可以参看下载内容)

下载文件列表

RAM(Verilog)/db/altsyncram_8oc1.tdf
RAM(Verilog)/db/altsyncram_i741.tdf
RAM(Verilog)/db/logic_util_heursitic.dat
RAM(Verilog)/db/prev_cmp_RAM.asm.qmsg
RAM(Verilog)/db/prev_cmp_RAM.fit.qmsg
RAM(Verilog)/db/prev_cmp_RAM.map.qmsg
RAM(Verilog)/db/prev_cmp_RAM.qmsg
RAM(Verilog)/db/prev_cmp_RAM.sim.qmsg
RAM(Verilog)/db/prev_cmp_RAM.tan.qmsg
RAM(Verilog)/db/RAM.(0).cnf.cdb
RAM(Verilog)/db/RAM.(0).cnf.hdb
RAM(Verilog)/db/RAM.(1).cnf.cdb
RAM(Verilog)/db/RAM.(1).cnf.hdb
RAM(Verilog)/db/RAM.(2).cnf.cdb
RAM(Verilog)/db/RAM.(2).cnf.hdb
RAM(Verilog)/db/RAM.(3).cnf.cdb
RAM(Verilog)/db/RAM.(3).cnf.hdb
RAM(Verilog)/db/RAM.(4).cnf.cdb
RAM(Verilog)/db/RAM.(4).cnf.hdb
RAM(Verilog)/db/RAM.analyze_file.qmsg
RAM(Verilog)/db/RAM.asm.qmsg
RAM(Verilog)/db/RAM.asm.rdb
RAM(Verilog)/db/RAM.asm_labs.ddb
RAM(Verilog)/db/RAM.cbx.xml
RAM(Verilog)/db/RAM.cmp.bpm
RAM(Verilog)/db/RAM.cmp.cdb
RAM(Verilog)/db/RAM.cmp.ecobp
RAM(Verilog)/db/RAM.cmp.hdb
RAM(Verilog)/db/RAM.cmp.kpt
RAM(Verilog)/db/RAM.cmp.logdb
RAM(Verilog)/db/RAM.cmp.rdb
RAM(Verilog)/db/RAM.cmp.tdb
RAM(Verilog)/db/RAM.cmp0.ddb
RAM(Verilog)/db/RAM.cmp_merge.kpt
RAM(Verilog)/db/RAM.db_info
RAM(Verilog)/db/RAM.eco.cdb
RAM(Verilog)/db/RAM.eds_overflow
RAM(Verilog)/db/RAM.fit.qmsg
RAM(Verilog)/db/RAM.fnsim.hdb
RAM(Verilog)/db/RAM.fnsim.qmsg
RAM(Verilog)/db/RAM.hier_info
RAM(Verilog)/db/RAM.hif
RAM(Verilog)/db/RAM.lpc.html
RAM(Verilog)/db/RAM.lpc.rdb
RAM(Verilog)/db/RAM.lpc.txt
RAM(Verilog)/db/RAM.map.bpm
RAM(Verilog)/db/RAM.map.cdb
RAM(Verilog)/db/RAM.map.ecobp
RAM(Verilog)/db/RAM.map.hdb
RAM(Verilog)/db/RAM.map.kpt
RAM(Verilog)/db/RAM.map.logdb
RAM(Verilog)/db/RAM.map.qmsg
RAM(Verilog)/db/RAM.map_bb.cdb
RAM(Verilog)/db/RAM.map_bb.hdb
RAM(Verilog)/db/RAM.map_bb.logdb
RAM(Verilog)/db/RAM.pre_map.cdb
RAM(Verilog)/db/RAM.pre_map.hdb
RAM(Verilog)/db/RAM.rtlv.hdb
RAM(Verilog)/db/RAM.rtlv_sg.cdb
RAM(Verilog)/db/RAM.rtlv_sg_swap.cdb
RAM(Verilog)/db/RAM.sgdiff.cdb
RAM(Verilog)/db/RAM.sgdiff.hdb
RAM(Verilog)/db/RAM.sim.cvwf
RAM(Verilog)/db/RAM.sim.hdb
RAM(Verilog)/db/RAM.sim.qmsg
RAM(Verilog)/db/RAM.sim.rdb
RAM(Verilog)/db/RAM.simfam
RAM(Verilog)/db/RAM.sld_design_entry.sci
RAM(Verilog)/db/RAM.sld_design_entry_dsc.sci
RAM(Verilog)/db/RAM.smart_action.txt
RAM(Verilog)/db/RAM.syn_hier_info
RAM(Verilog)/db/RAM.tan.qmsg
RAM(Verilog)/db/RAM.tis_db_list.ddb
RAM(Verilog)/db/RAM.tmw_info
RAM(Verilog)/db/wed.wsf
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.cdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.dfp
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.hdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.kpt
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.logdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.rcfdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.cmp.re.rcfdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.map.cdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.map.dpi
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.map.hdb
RAM(Verilog)/incremental_db/compiled_partitions/RAM.root_partition.map.kpt
RAM(Verilog)/incremental_db/README
RAM(Verilog)/RAM.asm.rpt
RAM(Verilog)/RAM.done
RAM(Verilog)/RAM.dpf
RAM(Verilog)/RAM.fit.rpt
RAM(Verilog)/RAM.fit.smsg
RAM(Verilog)/RAM.fit.summary
RAM(Verilog)/RAM.flow.rpt
RAM(Verilog)/RAM.map.rpt
RAM(Verilog)/RAM.map.summary
RAM(Verilog)/RAM.pin
RAM(Verilog)/RAM.pof
RAM(Verilog)/RAM.qpf
RAM(Verilog)/RAM.qsf
RAM(Verilog)/RAM.qws
RAM(Verilog)/RAM.sim.rpt
RAM(Verilog)/RAM.sof
RAM(Verilog)/RAM.tan.rpt
RAM(Verilog)/RAM.tan.summary
RAM(Verilog)/RAM.v
RAM(Verilog)/RAM.v.bak
RAM(Verilog)/RAM.vwf
RAM(LPM)/db/altsyncram_ne81.tdf
RAM(LPM)/db/logic_util_heursitic.dat
RAM(LPM)/db/prev_cmp_RAM.asm.qmsg
RAM(LPM)/db/prev_cmp_RAM.fit.qmsg
RAM(LPM)/db/prev_cmp_RAM.map.qmsg
RAM(LPM)/db/prev_cmp_RAM.qmsg
RAM(LPM)/db/prev_cmp_RAM.tan.qmsg
RAM(LPM)/db/RAM.(0).cnf.cdb
RAM(LPM)/db/RAM.(0).cnf.hdb
RAM(LPM)/db/RAM.(1).cnf.cdb
RAM(LPM)/db/RAM.(1).cnf.hdb
RAM(LPM)/db/RAM.(2).cnf.cdb
RAM(LPM)/db/RAM.(2).cnf.hdb
RAM(LPM)/db/RAM.analyze_file.qmsg
RAM(LPM)/db/RAM.asm.qmsg
RAM(LPM)/db/RAM.asm.rdb
RAM(LPM)/db/RAM.cbx.xml
RAM(LPM)/db/RAM.cmp.ecobp
RAM(LPM)/db/RAM.cmp.kpt
RAM(LPM)/db/RAM.cmp.rdb
RAM(LPM)/db/RAM.cmp0.ddb
RAM(LPM)/db/RAM.cmp_merge.kpt
RAM(LPM)/db/RAM.db_info
RAM(LPM)/db/RAM.eco.cdb
RAM(LPM)/db/RAM.fit.qmsg
RAM(LPM)/db/RAM.hier_info
RAM(LPM)/db/RAM.hif
RAM(LPM)/db/RAM.lpc.html
RAM(LPM)/db/RAM.lpc.rdb
RAM(LPM)/db/RAM.lpc.txt
RAM(LPM)/db/RAM.map.ecobp
RAM(LPM)/db/RAM.map.kpt
RAM(LPM)/db/RAM.map.qmsg
RAM(LPM)/db/RAM.map_bb.hdb
RAM(LPM)/db/RAM.pre_map.cdb
RAM(LPM)/db/RAM.pre_map.hdb
RAM(LPM)/db/RAM.rtlv.hdb
RAM(LPM)/db/RAM.rtlv_sg.cdb
RAM(LPM)/db/RAM.rtlv_sg_swap.cdb
RAM(LPM)/db/RAM.sgdiff.cdb
RAM(LPM)/db/RAM.sgdiff.hdb
RAM(LPM)/db/RAM.sld_design_entry.sci
RAM(LPM)/db/RAM.sld_design_entry_dsc.sci
RAM(LPM)/db/RAM.smart_action.txt
RAM(LPM)/db/RAM.syn_hier_info
RAM(LPM)/db/RAM.tan.qmsg
RAM(LPM)/db/RAM.tis_db_list.ddb
RAM(LPM)/incremental_db/compiled_partitions/RAM.root_partition.cmp.cdb

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