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文件名称:dds_synthesizer_latest.tar

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    2012-11-16
  • 文件大小:
    507.84kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

基于FPGA的DDS信号发生器,1-20Mhz。调试通过。-FPGA-based DDS signal generator ,1-20Mhz. Through debugging.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

dds_synthesizer/
dds_synthesizer/tags/
dds_synthesizer/branches/
dds_synthesizer/trunk/
dds_synthesizer/trunk/doc/
dds_synthesizer/trunk/doc/images/
dds_synthesizer/trunk/doc/images/build.sh
dds_synthesizer/trunk/doc/images/dds_implementation.svg
dds_synthesizer/trunk/doc/images/dds_implementation.pdf
dds_synthesizer/trunk/doc/images/dds_implementation.eps
dds_synthesizer/trunk/doc/dds_synthesizer.tex
dds_synthesizer/trunk/doc/dds_synthesizer.pdf
dds_synthesizer/trunk/copying
dds_synthesizer/trunk/sim/
dds_synthesizer/trunk/sim/dds_synthesizer.mpf
dds_synthesizer/trunk/sim/dds_synthesizer.cr.mti
dds_synthesizer/trunk/sim/vsim.wlf
dds_synthesizer/trunk/sim/WAVEFORMS/
dds_synthesizer/trunk/sim/WAVEFORMS/dds_synthesizer.do
dds_synthesizer/trunk/sim/transcript
dds_synthesizer/trunk/vhdl/
dds_synthesizer/trunk/vhdl/dds_synthesizer.vhd
dds_synthesizer/trunk/vhdl/dds_synthesizer_tb.vhd
dds_synthesizer/trunk/vhdl/sine_lut/
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_10_x_12.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_16_x_14.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_14_x_10.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_16.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_16_x_10.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_14_x_12.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_14_x_14.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_16.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_16_x_16.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_14_x_8.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_10.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_10_x_16.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_14.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_14.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_8.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_10_x_14.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_8.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_10_x_10.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_14_x_16.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_16_x_8.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_12.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_10_x_8.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_10.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_12.vhd
dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_16_x_12.vhd
dds_synthesizer/trunk/matlab/
dds_synthesizer/trunk/matlab/generate_vhdl_lut.m
dds_synthesizer/trunk/matlab/sine_lut_gen.m
dds_synthesizer/trunk/matlab/sine_lut.m
dds_synthesizer/web_uploads/
dds_synthesizer/web_uploads/thumb_dds_implementation.png
dds_synthesizer/web_uploads/dds_implementation.png

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