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文件名称:FlashROM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-03-08
  • 文件大小：
    386.21kb
  • 已下载：
    0次
  • 提 供 者：
    x****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

周立功Fusion StartKit，fpga开发板的实验例程，FlashROM实验-ZLG Fusion StartKit, fpga development board test routines, FlashROM experiment
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FlashROM实验/Project/Flash_ROM/constraint/Flash_ROM_Top.pdc
FlashROM实验/Project/Flash_ROM/designer/impl1/designer.log
FlashROM实验/Project/Flash_ROM/designer/impl1/designer_genhdl.log
FlashROM实验/Project/Flash_ROM/designer/impl1/designer_gen_ba.log
FlashROM实验/Project/Flash_ROM/designer/impl1/FlashROM16.tcl
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.adb
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.dtf/verify.log
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.ide_des
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.pdb
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.pdb.depends
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top.tcl
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top_ba.sdf
FlashROM实验/Project/Flash_ROM/designer/impl1/Flash_ROM_Top_ba.v
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/@flash_@r@o@m_@top/verilog.psm
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/@flash_@r@o@m_@top/_primary.dat
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/@flash_@r@o@m_@top/_primary.vhd
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/verilog.psm
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/_primary.dat
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/testbench/verilog.psm
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/testbench/_primary.dat
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/testbench/_primary.vhd
FlashROM实验/Project/Flash_ROM/designer/impl1/simulation/postlayout/_info
FlashROM实验/Project/Flash_ROM/Flash_ROM.prj
FlashROM实验/Project/Flash_ROM/hdl/FlashROM_Out.v
FlashROM实验/Project/Flash_ROM/hdl/Flash_ROM_Ctr.v
FlashROM实验/Project/Flash_ROM/hdl/Flash_ROM_Top.v
FlashROM实验/Project/Flash_ROM/hdl/hdlsynchk.tcl
FlashROM实验/Project/Flash_ROM/simulation/FlashROM16.mem
FlashROM实验/Project/Flash_ROM/simulation/meminit.dat
FlashROM实验/Project/Flash_ROM/simulation/modelsim.ini
FlashROM实验/Project/Flash_ROM/simulation/modelsim.ini.sav
FlashROM实验/Project/Flash_ROM/simulation/modelsim.log
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m16/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m16/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m16/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m_@out/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m_@out/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash@r@o@m_@out/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@ctr/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@ctr/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@ctr/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/_info
FlashROM实验/Project/Flash_ROM/simulation/vsim.wlf
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.cxf
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.gen
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.log
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.mem
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.ufc
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.v
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/hdlsynchk.tcl
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16_work.ixf
FlashROM实验/Project/Flash_ROM/smartgen/smartgen.aws
FlashROM实验/Project/Flash_ROM/stimulus/BtimErrors.log
FlashROM实验/Project/Flash_ROM/stimulus/files_to_build.txt
FlashROM实验/Project/Flash_ROM/stimulus/Flash_ROM_Top.dsk
FlashROM实验/Project/Flash_ROM/stimulus/Flash_ROM_Top.hpj
FlashROM实验/Project/Flash_ROM/stimulus/waveperl.log
FlashROM实验/Project/Flash_ROM/synthesis/.recordref
FlashROM实验/Projec

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