文件名称:bch_dec
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- 上传时间：2013-04-18
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文件大小：1.05mb
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BCH编解码
Features :
– allows to correct up to 2 errors.
– supports 16/32/64/128 bit memories (typical memory word sizes).
– operates on complete memory words in a single cycle.
– pure combinational logic design-The double error correcting (DEC) BCH encoder/decoder IP cores.
Features :
– allows to correct up to 2 errors.
– supports 16/32/64/128 bit memories (typical memory word sizes).
– operates on complete memory words in a single cycle.
– pure combinational logic design-The double error correcting (DEC) BCH encoder/decoder IP cores.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Tmp/bch_dec_for_opencores/src/
Tmp/bch_dec_for_opencores/src/doc/
Tmp/bch_dec_for_opencores/src/doc/bch_dec_dcd.pdf
Tmp/bch_dec_for_opencores/src/rtl/
Tmp/bch_dec_for_opencores/src/rtl/univ/
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_dcd_univ_top.v
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_enc_univ_top.v
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_fn.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_calc_univ.v
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_127.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_255.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_31.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_63.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_127.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_255.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_31.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_63.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_pat_dcd_rom_univ.v
Tmp/bch_dec_for_opencores/src/rtl/univ/timescale.vh
Tmp/bch_dec_for_opencores/src/sim/
Tmp/bch_dec_for_opencores/src/sim/univ/
Tmp/bch_dec_for_opencores/src/sim/univ/dcd_univ_tb_top_n.v
Tmp/bch_dec_for_opencores/src/doc/
Tmp/bch_dec_for_opencores/src/doc/bch_dec_dcd.pdf
Tmp/bch_dec_for_opencores/src/rtl/
Tmp/bch_dec_for_opencores/src/rtl/univ/
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_dcd_univ_top.v
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_enc_univ_top.v
Tmp/bch_dec_for_opencores/src/rtl/univ/bch_dec_fn.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_calc_univ.v
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_127.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_255.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_31.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/enc_synd_gen_fn_63.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_127.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_255.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_31.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_patt_dcd_fn_63.vh
Tmp/bch_dec_for_opencores/src/rtl/univ/err_pat_dcd_rom_univ.v
Tmp/bch_dec_for_opencores/src/rtl/univ/timescale.vh
Tmp/bch_dec_for_opencores/src/sim/
Tmp/bch_dec_for_opencores/src/sim/univ/
Tmp/bch_dec_for_opencores/src/sim/univ/dcd_univ_tb_top_n.v
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