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文件名称:counter10

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    2013-08-03
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    124.81kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

verilog编写的10进制计数器,并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
(系统自动生成,下载前可以参看下载内容)

下载文件列表

counter10/counter10.qpf
counter10/counter10.qsf
counter10/db/counter10.db_info
counter10/db/prev_cmp_counter10.qmsg
counter10/db/counter10.tis_db_list.ddb
counter10/db/counter10.eda.qmsg
counter10/db/counter10.(0).cnf.cdb
counter10/db/counter10.(0).cnf.hdb
counter10/db/logic_util_heursitic.dat
counter10/db/counter10.rtlv_sg_swap.cdb
counter10/db/counter10.cbx.xml
counter10/db/counter10.lpc.txt
counter10/db/counter10.lpc.html
counter10/db/counter10.map.qmsg
counter10/db/counter10.smart_action.txt
counter10/db/counter10.lpc.rdb
counter10/db/counter10.sld_design_entry.sci
counter10/db/counter10.pre_map.hdb
counter10/db/counter10.pre_map.cdb
counter10/db/counter10.map_bb.logdb
counter10/db/counter10.sgdiff.cdb
counter10/db/counter10.sgdiff.hdb
counter10/db/counter10.rtlv_sg.cdb
counter10/db/counter10.rtlv.hdb
counter10/db/counter10.hif
counter10/db/counter10.sld_design_entry_dsc.sci
counter10/db/counter10.hier_info
counter10/db/counter10.map.cdb
counter10/db/counter10.map_bb.cdb
counter10/db/counter10.map.hdb
counter10/db/counter10.map_bb.hdb
counter10/db/counter10.map.logdb
counter10/db/counter10.map.bpm
counter10/db/counter10.cmp.rdb
counter10/db/counter10.cmp.hdb
counter10/db/counter10.syn_hier_info
counter10/db/counter10.map.kpt
counter10/db/counter10.cmp_merge.kpt
counter10/counter10.v
counter10/release/counter10.map.summary
counter10/release/counter10.done
counter10/release/counter10.map.rpt
counter10/release/counter10.eda.rpt
counter10/release/counter10.flow.rpt
counter10/counter10.v.bak
counter10/incremental_db/compiled_partitions/counter10.db_info
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.kpt
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.hbdb.hb_info
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.hbdb.sig
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.dpi
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.cdb
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.hdb
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.hbdb.cdb
counter10/incremental_db/compiled_partitions/counter10.root_partition.map.hbdb.hdb
counter10/incremental_db/README
counter10/work/_info
counter10/simulation/modelsim/counter10.vt
counter10/simulation/modelsim/counter10_run_msim_rtl_verilog.do
counter10/simulation/modelsim/msim_transcript
counter10/simulation/modelsim/rtl_work/_info
counter10/simulation/modelsim/rtl_work/_vmake
counter10/simulation/modelsim/rtl_work/counter10/_primary.vhd
counter10/simulation/modelsim/rtl_work/counter10/verilog.psm
counter10/simulation/modelsim/rtl_work/counter10/verilog.prw
counter10/simulation/modelsim/rtl_work/counter10/_primary.dbs
counter10/simulation/modelsim/rtl_work/counter10/_primary.dat
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst/_primary.vhd
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst/verilog.psm
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst/verilog.prw
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst/_primary.dbs
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst/_primary.dat
counter10/simulation/modelsim/modelsim.ini
counter10/simulation/modelsim/vsim.wlf
counter10/counter10_nativelink_simulation.rpt
counter10/simulation/modelsim/rtl_work/_temp
counter10/simulation/modelsim/rtl_work/counter10
counter10/simulation/modelsim/rtl_work/counter10_vlg_tst
counter10/simulation/modelsim/rtl_work
counter10/incremental_db/compiled_partitions
counter10/simulation/modelsim
counter10/db
counter10/release
counter10/incremental_db
counter10/work
counter10/simulation
counter10

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