CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程

文件名称:add

  • 所属分类:
  • 标签属性:
  • 上传时间:
    2014-04-08
  • 文件大小:
    1.47mb
  • 已下载:
    0次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog 语言 加法器仿真调试过,没有任何问题 很简单的FPGA入门。-Verilog adder
(系统自动生成,下载前可以参看下载内容)

下载文件列表

add/add.done
add/add.eda.rpt
add/add.flow.rpt
add/add.map.rpt
add/add.map.summary
add/add.qpf
add/add.qsf
add/add.v
add/add.v.bak
add/add_nativelink_simulation.rpt
add/db/add.(0).cnf.cdb
add/db/add.(0).cnf.hdb
add/db/add.cbx.xml
add/db/add.cmp.hdb
add/db/add.cmp.rdb
add/db/add.db_info
add/db/add.eda.qmsg
add/db/add.hier_info
add/db/add.hif
add/db/add.lpc.html
add/db/add.lpc.rdb
add/db/add.lpc.txt
add/db/add.map.cdb
add/db/add.map.hdb
add/db/add.map.logdb
add/db/add.map.qmsg
add/db/add.pre_map.cdb
add/db/add.pre_map.hdb
add/db/add.rtlv.hdb
add/db/add.rtlv_sg.cdb
add/db/add.rtlv_sg_swap.cdb
add/db/add.sgdiff.cdb
add/db/add.sgdiff.hdb
add/db/add.sld_design_entry.sci
add/db/add.sld_design_entry_dsc.sci
add/db/add.smart_action.txt
add/db/add.syn_hier_info
add/db/add.tis_db_list.ddb
add/db/logic_util_heursitic.dat
add/db/prev_cmp_add.qmsg
add/incremental_db/compiled_partitions/add.db_info
add/incremental_db/compiled_partitions/add.root_partition.map.kpt
add/incremental_db/README
add/simulation/modelsim/add.vt
add/simulation/modelsim/add.vt.bak
add/simulation/modelsim/add_run_msim_rtl_verilog.do
add/simulation/modelsim/add_run_msim_rtl_verilog.do.bak
add/simulation/modelsim/msim_transcript
add/simulation/modelsim/rtl_work/@_opt/vopt22ajhw
add/simulation/modelsim/rtl_work/@_opt/vopt2deniv
add/simulation/modelsim/rtl_work/@_opt/vopt664ifv
add/simulation/modelsim/rtl_work/@_opt/vopt6z0g2w
add/simulation/modelsim/rtl_work/@_opt/vopt9rnczv
add/simulation/modelsim/rtl_work/@_opt/voptdyd9dv
add/simulation/modelsim/rtl_work/@_opt/voptg7030w
add/simulation/modelsim/rtl_work/@_opt/voptgvn6yk
add/simulation/modelsim/rtl_work/@_opt/voptkbc3yk
add/simulation/modelsim/rtl_work/@_opt/voptkqm00w
add/simulation/modelsim/rtl_work/@_opt/voptq7bxzv
add/simulation/modelsim/rtl_work/@_opt/voptqq7tmw
add/simulation/modelsim/rtl_work/@_opt/voptv7xqmw
add/simulation/modelsim/rtl_work/@_opt/voptvd1w7w
add/simulation/modelsim/rtl_work/@_opt/voptvq0szv
add/simulation/modelsim/rtl_work/@_opt/voptyqikmw
add/simulation/modelsim/rtl_work/@_opt/voptz8knkw
add/simulation/modelsim/rtl_work/@_opt/voptzjrsmv
add/simulation/modelsim/rtl_work/@_opt/_deps
add/simulation/modelsim/rtl_work/add/_primary.dat
add/simulation/modelsim/rtl_work/add/_primary.dbs
add/simulation/modelsim/rtl_work/add/_primary.vhd
add/simulation/modelsim/rtl_work/add_vlg_tst/_primary.dat
add/simulation/modelsim/rtl_work/add_vlg_tst/_primary.dbs
add/simulation/modelsim/rtl_work/add_vlg_tst/_primary.vhd
add/simulation/modelsim/rtl_work/_info
add/simulation/modelsim/rtl_work/_vmake
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.vhd
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dat
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dbs
add/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台,只提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度。更多...
  • 本站已设置防盗链,请勿用迅雷、QQ旋风等下载软件下载资源,下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或换浏览器;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*快速评论: 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内  容:
*验 证 码:
搜珍网 www.dssz.com