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文件名称:DDS

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    2014-05-11
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    4.28mb
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本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术(DDS)是一种先进的电路结构,能在全数字下对输出信号频率进行精确而快速的控制,DDS技术还在解决输出信号频率增量选择方面具有很好的应用,DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。 文中介绍了DDS的基本原理,对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器,。完成了软件和硬件的设计,以及实验样机的部分调试。-The design is based digital frequency synthesizer technology, using a sine lookup table to achieve waveform generation. Direct digital frequency synthesis (DDS) is an advanced circuit structure can fully digital output signal frequency under precise and fast control, DDS technology also solve the incremental output signal frequency selection signal having a very good application, DDS generated by high frequency resolution, frequency switching speed, phase-continuous frequency switching time, low phase noise output and can generate arbitrary waveforms, and many other advantages . This paper introduces the basic principles of the DDS, DDS MS for its bulk inhibition were analyzed. Programming using ultra high-speed hardware descr iption language VHDL descr iption DDS, on the basis of the design of the sine wave, triangle wave, square wave signal generator. Completed part of debugging software and hardware design, and the experimental prototype.
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下载文件列表

DDS/
DDS/control.v
DDS/counter.v
DDS/counter.v.bak
DDS/db/
DDS/db/altsyncram_1191.tdf
DDS/db/altsyncram_fs81.tdf
DDS/db/DSS.(0).cnf.cdb
DDS/db/DSS.(0).cnf.hdb
DDS/db/DSS.(1).cnf.cdb
DDS/db/DSS.(1).cnf.hdb
DDS/db/DSS.(2).cnf.cdb
DDS/db/DSS.(2).cnf.hdb
DDS/db/DSS.(3).cnf.cdb
DDS/db/DSS.(3).cnf.hdb
DDS/db/DSS.(4).cnf.cdb
DDS/db/DSS.(4).cnf.hdb
DDS/db/DSS.(5).cnf.cdb
DDS/db/DSS.(5).cnf.hdb
DDS/db/DSS.(6).cnf.cdb
DDS/db/DSS.(6).cnf.hdb
DDS/db/DSS.(7).cnf.cdb
DDS/db/DSS.(7).cnf.hdb
DDS/db/DSS.(8).cnf.cdb
DDS/db/DSS.(8).cnf.hdb
DDS/db/DSS.ae.hdb
DDS/db/DSS.amm.cdb
DDS/db/DSS.asm.qmsg
DDS/db/DSS.asm.rdb
DDS/db/DSS.asm_labs.ddb
DDS/db/DSS.cbx.xml
DDS/db/DSS.cmp.bpm
DDS/db/DSS.cmp.cdb
DDS/db/DSS.cmp.hdb
DDS/db/DSS.cmp.kpt
DDS/db/DSS.cmp.logdb
DDS/db/DSS.cmp.rdb
DDS/db/DSS.cmp0.ddb
DDS/db/DSS.cmp1.ddb
DDS/db/DSS.cmp_merge.kpt
DDS/db/DSS.db_info
DDS/db/DSS.eda.qmsg
DDS/db/DSS.fit.qmsg
DDS/db/DSS.hier_info
DDS/db/DSS.hif
DDS/db/DSS.idb.cdb
DDS/db/DSS.lpc.html
DDS/db/DSS.lpc.rdb
DDS/db/DSS.lpc.txt
DDS/db/DSS.map.bpm
DDS/db/DSS.map.cdb
DDS/db/DSS.map.hdb
DDS/db/DSS.map.kpt
DDS/db/DSS.map.logdb
DDS/db/DSS.map.qmsg
DDS/db/DSS.map.rdb
DDS/db/DSS.map_bb.cdb
DDS/db/DSS.map_bb.hdb
DDS/db/DSS.map_bb.logdb
DDS/db/DSS.pre_map.cdb
DDS/db/DSS.pre_map.hdb
DDS/db/DSS.root_partition.map.reg_db.cdb
DDS/db/DSS.routing.rdb
DDS/db/DSS.rtlv.hdb
DDS/db/DSS.rtlv_sg.cdb
DDS/db/DSS.rtlv_sg_swap.cdb
DDS/db/DSS.sgdiff.cdb
DDS/db/DSS.sgdiff.hdb
DDS/db/DSS.sim.cvwf
DDS/db/DSS.sld_design_entry.sci
DDS/db/DSS.sld_design_entry_dsc.sci
DDS/db/DSS.smart_action.txt
DDS/db/DSS.sta.qmsg
DDS/db/DSS.sta.rdb
DDS/db/DSS.syn_hier_info
DDS/db/DSS.tis_db_list.ddb
DDS/db/DSS.tmw_info
DDS/db/logic_util_heursitic.dat
DDS/db/prev_cmp_DSS.asm.qmsg
DDS/db/prev_cmp_DSS.eda.qmsg
DDS/db/prev_cmp_DSS.fit.qmsg
DDS/db/prev_cmp_DSS.map.qmsg
DDS/db/prev_cmp_DSS.qmsg
DDS/db/prev_cmp_DSS.tan.qmsg
DDS/db/wed.wsf
DDS/DSS.asm.rpt
DDS/DSS.done
DDS/DSS.eda.rpt
DDS/DSS.fit.rpt
DDS/DSS.fit.smsg
DDS/DSS.fit.summary
DDS/DSS.flow.rpt
DDS/DSS.jdi
DDS/DSS.map.rpt
DDS/DSS.map.summary
DDS/DSS.pin
DDS/DSS.pof
DDS/DSS.qpf
DDS/DSS.qsf
DDS/DSS.qws
DDS/DSS.sim.rpt
DDS/DSS.sof
DDS/DSS.sta.rpt
DDS/DSS.sta.summary
DDS/DSS.tan.rpt
DDS/DSS.tan.summary
DDS/DSS.v
DDS/DSS.v.bak
DDS/DSS.vwf
DDS/DSS_assignment_defaults.qdf
DDS/DSS_description.txt
DDS/DSS_nativelink_simulation.rpt
DDS/greybox_tmp/
DDS/greybox_tmp/cbx_args.txt
DDS/incremental_db/
DDS/incremental_db/compiled_partitions/
DDS/incremental_db/compiled_partitions/DSS.db_info
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.cdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.dfp
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.hdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.kpt
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.logdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.cmp.rcfdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.cdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.dpi
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.hbdb.cdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.hbdb.hb_info
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.hbdb.hdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.hbdb.sig
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.hdb
DDS/incremental_db/compiled_partitions/DSS.root_partition.map.kpt
DDS/incremental_db/README
DDS/rom.mif
DDS/rom.qip
DDS/rom.v
DDS/rom_bb.v
DDS/rom_inst.v
DDS/simulation/
DDS/simulation/modelsim/
DDS/simulation/modelsim/DDS.vt
DDS/simulation/modelsim/DDS.vt.bak
DDS/simulation/modelsim/DSS.sft
DDS/simulation/modelsim/DSS.vo
DDS/simulation/modelsim/DSS_8_1200mv_0c_slow.vo
DDS/simulation/modelsim/DSS_8_1200mv_0c_v_slow.sdo
DDS/simulation/modelsim/DSS_8_1200mv_85c_slow.vo
DDS/simulation/modelsim/DSS_8_1200mv_85c_v_slow.sdo
DDS/simulation/modelsim/DSS_fast.vo
DDS/simulation/modelsim/DSS_min_1200mv_0c_fast.vo
DDS/simulation/modelsim/DSS_min_1200mv_0c_v_fast.sdo
DDS/simulation/modelsim/DSS_modelsim.xrf
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak1
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak2
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak3
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak4
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak5
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak6
DDS/simulation/modelsim/DSS_run_msim_rtl_verilog.do.bak7
DDS/simulation/modelsim/DSS_v.sdo
DDS/simulation/modelsim/DSS_v_fast.sdo
DDS/simulation/modelsim/modelsim.ini
DDS/simulation/modelsim/msim_transcript
DDS/simulation/modelsim/rom.mif
DDS/simulation/modelsim/rom.ver
DDS/simulation/modelsim/rtl_work/
DDS/simulation/modelsim/rtl_work/@d@d@s/
DDS/simulation/modelsim/rtl_work/@d@d@s/verilog.prw
DDS/simulation/modelsim/rtl_work/@d@d@s/verilog.psm
DDS/simulation/modelsim/rtl_work/@d@d@s/_primary.dat
DDS/simulation/modelsim/rtl_work/@d@d@s/_primary.dbs
DDS/simulation/modelsim/rtl_work/@d@d@s/_prima

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