文件名称:dsp
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- 上传时间：2015-04-14
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文件大小：29.59kb
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DSP Architechture using Verilog. (the concept of the programm differ the original)-DSP Architechture using Verilog. (the concept of the programm differ the original)
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下载文件列表
_xmsgs/pn_parser.xmsgs
_xmsgs/xst.xmsgs
iseconfig/dsp.projectmgr
iseconfig/sensor.xreport
iseconfig/sensor_top.xreport
xst/work/work.sdbl
xst/work/work.sdbx
BaudRateGen.v
BaudRateGen_summary.html
dsp.gise
dsp.xise
INT_SRC.v
master.lso
master.prj
master.stx
master.xst
pfxadd.v
pfxint.v
s1.v
sensor.lso
sensor.prj
sensor.stx
sensor.xst
sensor_summary.html
sensor_top.v
sensor_top_summary.html
sensordecoder.v
sensorencoder.v
slave.lso
slave.prj
slave.stx
slave.xst
xst/projnav.tmp
xst/work
_xmsgs
ipcore_dir
iseconfig
xst
_xmsgs/xst.xmsgs
iseconfig/dsp.projectmgr
iseconfig/sensor.xreport
iseconfig/sensor_top.xreport
xst/work/work.sdbl
xst/work/work.sdbx
BaudRateGen.v
BaudRateGen_summary.html
dsp.gise
dsp.xise
INT_SRC.v
master.lso
master.prj
master.stx
master.xst
pfxadd.v
pfxint.v
s1.v
sensor.lso
sensor.prj
sensor.stx
sensor.xst
sensor_summary.html
sensor_top.v
sensor_top_summary.html
sensordecoder.v
sensorencoder.v
slave.lso
slave.prj
slave.stx
slave.xst
xst/projnav.tmp
xst/work
_xmsgs
ipcore_dir
iseconfig
xst
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