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文件名称:VerilogUart

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-09-21
  • 文件大小：
    946.45kb
  • 已下载：
    0次
  • 提 供 者：
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VerilogUart/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.cxf
VerilogUart/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
VerilogUart/component/work/DESIGN_IO/DESIGN_IO.cxf
VerilogUart/component/work/DESIGN_IO/DESIGN_IO.sdb
VerilogUart/component/work/UartSmartDesign/datasheet.xsl
VerilogUart/component/work/UartSmartDesign/drcss.xsl
VerilogUart/component/work/UartSmartDesign/UartSmartDesign.cxf
VerilogUart/component/work/UartSmartDesign/UartSmartDesign.sdb
VerilogUart/component/work/UartSmartDesign/UartSmartDesign.v
VerilogUart/component/work/UartSmartDesign/UartSmartDesign_DataSheet.xml
VerilogUart/component/work/UartSmartDesign/UartSmartDesign_DRC.xml
VerilogUart/component/work/UartSmartDesign/UartSmartDesign_manifest.txt
VerilogUart/constraint/UartSmartDesign_sdc.sdc
VerilogUart/designer/impl1/run_designer_tool.log
VerilogUart/designer/impl1/run_designer_tool.tcl
VerilogUart/designer/impl1/run_pinrpt.tcl
VerilogUart/designer/impl1/uart.ide_des
VerilogUart/designer/impl1/uart8n1.ide_des
VerilogUart/designer/impl1/UartSmartDesign.adb
VerilogUart/designer/impl1/UartSmartDesign.dtf/verify.log
VerilogUart/designer/impl1/UartSmartDesign.ide_des
VerilogUart/designer/impl1/UartSmartDesign.pdb
VerilogUart/designer/impl1/UartSmartDesign.pdb.depends
VerilogUart/designer/impl1/UartSmartDesign.tcl
VerilogUart/designer/impl1/UartSmartDesign_compile_log.rpt
VerilogUart/designer/impl1/UartSmartDesign_compile_report.txt
VerilogUart/designer/impl1/UartSmartDesign_fp/$$FlashPro_97574.L$$
VerilogUart/designer/impl1/UartSmartDesign_fp/projectData/UartSmartDesign.pdb
VerilogUart/designer/impl1/UartSmartDesign_fp/UartSmartDesign.pro
VerilogUart/designer/impl1/UartSmartDesign_fp/UartSmartDesign.tcl
VerilogUart/designer/impl1/UartSmartDesign_fp/UartSmartDesign_program.log
VerilogUart/designer/impl1/UartSmartDesign_fp.tcl
VerilogUart/designer/impl1/UartSmartDesign_globalnet_report.txt
VerilogUart/designer/impl1/UartSmartDesign_globalusage_report.txt
VerilogUart/designer/impl1/UartSmartDesign_iobank_report.txt
VerilogUart/designer/impl1/UartSmartDesign_maxdelay_timingviolations_report.txt
VerilogUart/designer/impl1/UartSmartDesign_maxdelay_timing_report.txt
VerilogUart/designer/impl1/UartSmartDesign_mindelay_timingviolations_report.txt
VerilogUart/designer/impl1/UartSmartDesign_mindelay_timing_report.txt
VerilogUart/designer/impl1/UartSmartDesign_placeroute_log.rpt
VerilogUart/designer/impl1/UartSmartDesign_place_and_route_report.txt
VerilogUart/designer/impl1/UartSmartDesign_prgdata_log.rpt
VerilogUart/designer/impl1/UartSmartDesign_report_pin_byname.txt
VerilogUart/designer/impl1/UartSmartDesign_report_pin_bynumber.txt
VerilogUart/designer/impl1/UartSmartDesign_timingconstraints_log.rpt
VerilogUart/designer/impl1/UartSmartDesign_verifytiming_log.rpt
VerilogUart/designer/impl1/UartTop.ide_des
VerilogUart/hdl/fifo8x15.v
VerilogUart/hdl/lowpass.v
VerilogUart/hdl/rst.v
VerilogUart/hdl/uart8n1_ctrl.v
VerilogUart/hdl/uart8n1_rx.v
VerilogUart/hdl/uart8n1_tx.v
VerilogUart/hdl/UartTop.v
VerilogUart/simulation/modelsim.ini
VerilogUart/simulation/modelsim.ini.sav
VerilogUart/smartgen/DESIGN_FIRMWARE_work.ixf
VerilogUart/smartgen/DESIGN_IO_work.ixf
VerilogUart/smartgen/PLL_core/PLL_core.cxf
VerilogUart/smartgen/PLL_core/PLL_core.gen
VerilogUart/smartgen/PLL_core/PLL_core.log
VerilogUart/smartgen/PLL_core/PLL_core.v
VerilogUart/smartgen/PLL_core_work.ixf
VerilogUart/smartgen/smartgen.aws
VerilogUart/smartgen/UartSmartDesign_work.ixf
VerilogUart/synthesis/.recordref_modgen
VerilogUart/synthesis/backup/uart8n1.srr
VerilogUart/synthesis/backup/UartSmartDesign.srr
VerilogUart/synthesis/dm/UartSmartDesign_comp.xdm
VerilogUart/synthesis/flatsch.srs
VerilogUart/synthesis/flatsch.sxr
VerilogUart/synthesis/run_options.txt
VerilogUart/synthesis/scratchproject.prs
VerilogUart/synthesis/stdout.log
VerilogUart/synthesis/sub___cin_w4.fdepxmr
VerilogUart/synthesis/synlog/constraint_check.rpt.rptmap
VerilogUart/synthesis/synlog/map.srr.rptmap
VerilogUart/synthesis/synlog/pre_map.srr.rptmap
VerilogUart/synthesis/synlog/report/uart8n1_compiler_errors.txt
VerilogUart/synthesis/synlog/report/uart8n1_compiler_notes.txt
VerilogUart/synthesis/synlog/report/uart8n1_compiler_runstatus.xml
VerilogUart/synthesis/synlog/report/UartSmartDesign_compiler_errors.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_compiler_notes.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_compiler_runstatus.xml
VerilogUart/synthesis/synlog/report/UartSmartDesign_compiler_warnings.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_constraint_check_job_errors.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_constraint_check_job_notes.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_constraint_check_job_runstatus.xml
VerilogUart/synthesis/synlog/report/UartSmartDesign_constraint_check_job_warnings.txt
VerilogUart/synthesis/synlog/report/UartSmartDesign_fpga_mapper_area_report.xml
VerilogUart/synthesis/synlog/report/UartSmartDesign_fpga_mapper_combined_clk.rpt
VerilogUart/synthesis/synlog/report/UartSmartDesign_fpga_mapper_errors.txt
VerilogUart/synthesis/synlog/report/UartS

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