文件名称:ex4_seg7
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- 上传时间：2016-01-04
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文件大小：142.78kb
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7 段数码管（ 不算小数点） 的原理也很简单， 它无非是由 7 个发光二极管组成。 这 7 个发光二极管有一个公共端， 必须接GND（ 共阴极数码管） 或者接 VCC（ 共阳极数码管）。 对7 个二极管的另一端进行控制， 相应的就能控制他们的亮暗。 不同的亮暗组合就产生了数字0-9 的显示效果。-7-segment (not counting the decimal point) is also very simple principle, it is nothing more than the seven light-emitting diodes. This seven light-emitting diodes have a common terminal, must be connected to GND (common cathode LED) or contact VCC (common anode LED). On the other end of the diode 7 is controlled accordingly will be able to control their light and dark. Different combinations of light and dark to produce a display of the numbers 0-9.
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下载文件列表
ex4_seg7/sm4205的管脚图和led段码表.txt
ex4_seg7/verilogled7/db/led_seg7.db_info
ex4_seg7/verilogled7/db/led_seg7.ipinfo
ex4_seg7/verilogled7/db/led_seg7.sld_design_entry.sci
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.asm.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.fit.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.map.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.tan.qmsg
ex4_seg7/verilogled7/incremental_db/compiled_partitions/led_seg7.db_info
ex4_seg7/verilogled7/incremental_db/compiled_partitions/led_seg7.root_partition.map.kpt
ex4_seg7/verilogled7/incremental_db/README
ex4_seg7/verilogled7/led_seg7.asm.rpt
ex4_seg7/verilogled7/led_seg7.cdf
ex4_seg7/verilogled7/led_seg7.done
ex4_seg7/verilogled7/led_seg7.dpf
ex4_seg7/verilogled7/led_seg7.fit.rpt
ex4_seg7/verilogled7/led_seg7.fit.smsg
ex4_seg7/verilogled7/led_seg7.fit.summary
ex4_seg7/verilogled7/led_seg7.flow.rpt
ex4_seg7/verilogled7/led_seg7.map.rpt
ex4_seg7/verilogled7/led_seg7.map.summary
ex4_seg7/verilogled7/led_seg7.pin
ex4_seg7/verilogled7/led_seg7.pof
ex4_seg7/verilogled7/led_seg7.qpf
ex4_seg7/verilogled7/led_seg7.qsf
ex4_seg7/verilogled7/led_seg7.qws
ex4_seg7/verilogled7/led_seg7.tan.rpt
ex4_seg7/verilogled7/led_seg7.tan.summary
ex4_seg7/verilogled7/led_seg7.v
ex4_seg7/verilogled7/led_seg7_assignment_defaults.qdf
ex4_seg7/数码管显示实验.pdf
ex4_seg7/verilogled7/incremental_db/compiled_partitions
ex4_seg7/verilogled7/db
ex4_seg7/verilogled7/incremental_db
ex4_seg7/verilogled7/output_files
ex4_seg7/verilogled7
ex4_seg7
ex4_seg7/verilogled7/db/led_seg7.db_info
ex4_seg7/verilogled7/db/led_seg7.ipinfo
ex4_seg7/verilogled7/db/led_seg7.sld_design_entry.sci
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.asm.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.fit.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.map.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.qmsg
ex4_seg7/verilogled7/db/prev_cmp_led_seg7.tan.qmsg
ex4_seg7/verilogled7/incremental_db/compiled_partitions/led_seg7.db_info
ex4_seg7/verilogled7/incremental_db/compiled_partitions/led_seg7.root_partition.map.kpt
ex4_seg7/verilogled7/incremental_db/README
ex4_seg7/verilogled7/led_seg7.asm.rpt
ex4_seg7/verilogled7/led_seg7.cdf
ex4_seg7/verilogled7/led_seg7.done
ex4_seg7/verilogled7/led_seg7.dpf
ex4_seg7/verilogled7/led_seg7.fit.rpt
ex4_seg7/verilogled7/led_seg7.fit.smsg
ex4_seg7/verilogled7/led_seg7.fit.summary
ex4_seg7/verilogled7/led_seg7.flow.rpt
ex4_seg7/verilogled7/led_seg7.map.rpt
ex4_seg7/verilogled7/led_seg7.map.summary
ex4_seg7/verilogled7/led_seg7.pin
ex4_seg7/verilogled7/led_seg7.pof
ex4_seg7/verilogled7/led_seg7.qpf
ex4_seg7/verilogled7/led_seg7.qsf
ex4_seg7/verilogled7/led_seg7.qws
ex4_seg7/verilogled7/led_seg7.tan.rpt
ex4_seg7/verilogled7/led_seg7.tan.summary
ex4_seg7/verilogled7/led_seg7.v
ex4_seg7/verilogled7/led_seg7_assignment_defaults.qdf
ex4_seg7/数码管显示实验.pdf
ex4_seg7/verilogled7/incremental_db/compiled_partitions
ex4_seg7/verilogled7/db
ex4_seg7/verilogled7/incremental_db
ex4_seg7/verilogled7/output_files
ex4_seg7/verilogled7
ex4_seg7
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