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文件名称:alu_1706_VHDLproject

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2016-05-24
  • 文件大小：
    1.9mb
  • 已下载：
    0次
  • 提 供 者：
    xia****
  • 相关连接：
    无
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常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，1.算术逻辑单元（alu_1706）,实现算术逻辑运算

2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。

3.全加器（full_adder）

4.半加器（half_adder）

5.3-8译码器（mutex_3to8）

6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic

2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).

3. The full adder (full_adder)

4. The half-adder (half_adder)

5.3-8 decoder (mutex_3to8)

6. Computer operator (S6) to achieve operator-related functions
(系统自动生成,下载前可以参看下载内容)

下载文件列表

alu_1706【VHDLproject】/alu_1706.qpf
alu_1706【VHDLproject】/alu_1706.qsf
alu_1706【VHDLproject】/alu_1706.qws
alu_1706【VHDLproject】/alu_1706.vhd
alu_1706【VHDLproject】/alu_1706.vhd.bak
alu_1706【VHDLproject】/db/alu_1706.(0).cnf.cdb
alu_1706【VHDLproject】/db/alu_1706.(0).cnf.hdb
alu_1706【VHDLproject】/db/alu_1706.asm.qmsg
alu_1706【VHDLproject】/db/alu_1706.asm.rdb
alu_1706【VHDLproject】/db/alu_1706.asm_labs.ddb
alu_1706【VHDLproject】/db/alu_1706.cbx.xml
alu_1706【VHDLproject】/db/alu_1706.cmp.bpm
alu_1706【VHDLproject】/db/alu_1706.cmp.cdb
alu_1706【VHDLproject】/db/alu_1706.cmp.hdb
alu_1706【VHDLproject】/db/alu_1706.cmp.idb
alu_1706【VHDLproject】/db/alu_1706.cmp.kpt
alu_1706【VHDLproject】/db/alu_1706.cmp.logdb
alu_1706【VHDLproject】/db/alu_1706.cmp.rdb
alu_1706【VHDLproject】/db/alu_1706.cmp_merge.kpt
alu_1706【VHDLproject】/db/alu_1706.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
alu_1706【VHDLproject】/db/alu_1706.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
alu_1706【VHDLproject】/db/alu_1706.db_info
alu_1706【VHDLproject】/db/alu_1706.eda.qmsg
alu_1706【VHDLproject】/db/alu_1706.fit.qmsg
alu_1706【VHDLproject】/db/alu_1706.hier_info
alu_1706【VHDLproject】/db/alu_1706.hif
alu_1706【VHDLproject】/db/alu_1706.ipinfo
alu_1706【VHDLproject】/db/alu_1706.lpc.html
alu_1706【VHDLproject】/db/alu_1706.lpc.rdb
alu_1706【VHDLproject】/db/alu_1706.lpc.txt
alu_1706【VHDLproject】/db/alu_1706.map.ammdb
alu_1706【VHDLproject】/db/alu_1706.map.bpm
alu_1706【VHDLproject】/db/alu_1706.map.cdb
alu_1706【VHDLproject】/db/alu_1706.map.hdb
alu_1706【VHDLproject】/db/alu_1706.map.kpt
alu_1706【VHDLproject】/db/alu_1706.map.logdb
alu_1706【VHDLproject】/db/alu_1706.map.qmsg
alu_1706【VHDLproject】/db/alu_1706.map.rdb
alu_1706【VHDLproject】/db/alu_1706.map_bb.cdb
alu_1706【VHDLproject】/db/alu_1706.map_bb.hdb
alu_1706【VHDLproject】/db/alu_1706.map_bb.logdb
alu_1706【VHDLproject】/db/alu_1706.pre_map.hdb
alu_1706【VHDLproject】/db/alu_1706.pti_db_list.ddb
alu_1706【VHDLproject】/db/alu_1706.root_partition.map.reg_db.cdb
alu_1706【VHDLproject】/db/alu_1706.routing.rdb
alu_1706【VHDLproject】/db/alu_1706.rtlv.hdb
alu_1706【VHDLproject】/db/alu_1706.rtlv_sg.cdb
alu_1706【VHDLproject】/db/alu_1706.rtlv_sg_swap.cdb
alu_1706【VHDLproject】/db/alu_1706.sgdiff.cdb
alu_1706【VHDLproject】/db/alu_1706.sgdiff.hdb
alu_1706【VHDLproject】/db/alu_1706.sld_design_entry.sci
alu_1706【VHDLproject】/db/alu_1706.sld_design_entry_dsc.sci
alu_1706【VHDLproject】/db/alu_1706.smart_action.txt
alu_1706【VHDLproject】/db/alu_1706.sta.qmsg
alu_1706【VHDLproject】/db/alu_1706.sta.rdb
alu_1706【VHDLproject】/db/alu_1706.sta_cmp.8_slow_1200mv_85c.tdb
alu_1706【VHDLproject】/db/alu_1706.syn_hier_info
alu_1706【VHDLproject】/db/alu_1706.tiscmp.fastest_slow_1200mv_0c.ddb
alu_1706【VHDLproject】/db/alu_1706.tiscmp.fastest_slow_1200mv_85c.ddb
alu_1706【VHDLproject】/db/alu_1706.tiscmp.fast_1200mv_0c.ddb
alu_1706【VHDLproject】/db/alu_1706.tiscmp.slow_1200mv_0c.ddb
alu_1706【VHDLproject】/db/alu_1706.tiscmp.slow_1200mv_85c.ddb
alu_1706【VHDLproject】/db/alu_1706.tis_db_list.ddb
alu_1706【VHDLproject】/db/alu_1706.vpr.ammdb
alu_1706【VHDLproject】/db/logic_util_heursitic.dat
alu_1706【VHDLproject】/db/prev_cmp_alu_1706.qmsg
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.db_info
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.ammdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.cdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.dfp
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.hdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.kpt
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.logdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.cmp.rcfdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.cdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.dpi
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.hbdb.cdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.hbdb.hb_info
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.hbdb.hdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.hbdb.sig
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.hdb
alu_1706【VHDLproject】/incremental_db/compiled_partitions/alu_1706.root_partition.map.kpt
alu_1706【VHDLproject】/incremental_db/README
alu_1706【VHDLproject】/output_files/alu_1706.asm.rpt
alu_1706【VHDLproject】/output_files/alu_1706.done
alu_1706【VHDLproject】/output_files/alu_1706.eda.rpt
alu_1706【VHDLproject】/output_files/alu_1706.fit.rpt
alu_1706【VHDLproject】/output_files/alu_1706.fit.smsg
alu_1706【VHDLproject】/output_files/alu_1706.fit.summary
alu_1706【VHDLproject】/output_files/alu_1706.flow.rpt
alu_1706【VHDLproject】/output_files/alu_1706.jdi
alu_1706【VHDLproject】/output_files/alu_1706.map.rpt
alu_1706【VHDLproject】/output_files/alu_1706.map.summary
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