含同步并行预置功能的8位移位寄存器。工作原理 当CLK的上升沿到来时进程被启动，如果这时预置使能LOAD为高电平，则将输入端口的8位二进制数并行置入移位寄存器中，作为串行右移输出的初始值；如果LOAD为低电平，则执行语句：

reg8（6 downto 0）< reg8(7 downto 1)-8 bit shift register with synchronous parallel preset function. The principle of work　when the rising edge of CLK when the process is started, if the preset enable LOAD to a high level, the 8 bit binary number will be in the input port of the parallel shift register, serial output shift as the initial value　if LOAD is low, then the statement is　d:

Reg8 (6 downto) < reg8 (7 downto 1)