74hc161.pdf
74hc161/
74hc161/74hc161.prj
74hc161/component/
74hc161/constraint/
74hc161/coreconsole/
74hc161/designer/
74hc161/designer/impl1/
74hc161/designer/impl1/count4.adb
74hc161/designer/impl1/count4.dtf/
74hc161/designer/impl1/count4.dtf/verify.log
74hc161/designer/impl1/count4.ide_des
74hc161/designer/impl1/count4.pdb
74hc161/designer/impl1/count4.pdb.depends
74hc161/designer/impl1/count4.tcl
74hc161/designer/impl1/count4_ba.sdf
74hc161/designer/impl1/count4_ba.v
74hc161/designer/impl1/count4_fp/
74hc161/designer/impl1/count4_fp/$$FlashPro_07294.L$$
74hc161/designer/impl1/count4_fp/count4.log
74hc161/designer/impl1/count4_fp/count4.pro
74hc161/designer/impl1/count4_fp/projectData/
74hc161/designer/impl1/count4_fp/projectData/count4.pdb
74hc161/designer/impl1/designer.log
74hc161/designer/impl1/designer_gen_ba.log
74hc161/designer/impl1/simulation/
74hc161/designer/impl1/testbench.ide_des
74hc161/hdl/
74hc161/hdl/74hc161.v
74hc161/phy_synthesis/
74hc161/simulation/
74hc161/simulation/modelsim.ini
74hc161/simulation/modelsim.ini.sav
74hc161/simulation/modelsim.log
74hc161/simulation/presynth/
74hc161/simulation/presynth/count4/
74hc161/simulation/presynth/count4/verilog.psm
74hc161/simulation/presynth/count4/_primary.dat
74hc161/simulation/presynth/count4/_primary.dbs
74hc161/simulation/presynth/count4/_primary.vhd
74hc161/simulation/presynth/testbench/
74hc161/simulation/presynth/testbench/verilog.psm
74hc161/simulation/presynth/testbench/_primary.dat
74hc161/simulation/presynth/testbench/_primary.dbs
74hc161/simulation/presynth/testbench/_primary.vhd
74hc161/simulation/presynth/_info
74hc161/simulation/presynth/_temp/
74hc161/simulation/presynth/_vmake
74hc161/simulation/run.do
74hc161/simulation/vsim.wlf
74hc161/smartgen/
74hc161/smartgen/smartgen.aws
74hc161/stimulus/
74hc161/stimulus/BtimErrors.log
74hc161/stimulus/count4.dsk
74hc161/stimulus/count4.hpj
74hc161/stimulus/files_to_build.txt
74hc161/stimulus/testbench.v
74hc161/stimulus/waveperl.log
74hc161/synthesis/
74hc161/synthesis/.recordref
74hc161/synthesis/AutoConstraint_count4.sdc
74hc161/synthesis/backup/
74hc161/synthesis/backup/count4.srr
74hc161/synthesis/coreip/
74hc161/synthesis/count4.areasrr
74hc161/synthesis/count4.edn
74hc161/synthesis/count4.fse
74hc161/synthesis/count4.htm
74hc161/synthesis/count4.map
74hc161/synthesis/count4.pdc
74hc161/synthesis/count4.sap
74hc161/synthesis/count4.sdf
74hc161/synthesis/count4.so
74hc161/synthesis/count4.srd
74hc161/synthesis/count4.srm
74hc161/synthesis/count4.srr
74hc161/synthesis/count4.srs
74hc161/synthesis/count4.szr
74hc161/synthesis/count4.tlg
74hc161/synthesis/count4_sdc.sdc
74hc161/synthesis/count4_syn.prd
74hc161/synthesis/count4_syn.prj
74hc161/synthesis/run_options.txt
74hc161/synthesis/stdout.log
74hc161/synthesis/syntmp/
74hc161/synthesis/syntmp/count4.plg
74hc161/synthesis/syntmp/count4_flink.htm
74hc161/synthesis/syntmp/count4_srr.htm
74hc161/synthesis/syntmp/count4_toc.htm
74hc161/synthesis/syntmp/sap.log
74hc161/synthesis/traplog.tlg
74hc161/viewdraw/
74hc161/viewdraw/sch/
74hc161/viewdraw/sym/
74hc161/viewdraw/vf/
74hc161/viewdraw/vf/project.lst
74hc161/viewdraw/viewdraw.ini
74hc161/viewdraw/wir/