搜索资源列表
8-Multipliers
- 国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。-Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
16bit-Mulitiplier-Verilog-procedure
- 这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器-This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier
booth_multiplier
- 从google上下载到的booth乘法器-booth multiplier
Booth-Multiplier-VHDL-Code
- 布斯乘法器 Booth Multiplier VHDL Code-Booth Multiplier VHDL Code
COP2000-experimental-instrument
- 计算机组成原理 利用COP2000实验仪自行设计指令系统实现乘法器和除法器实验指导-Principles of Computer Organization the use of COP2000 experimental instrument design their own instruction set multiplier and divider experimental guidance
multi16
- 有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。-Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace t
Verilog_divid
- vhdl语言描述传统除法器，传统乘法器的改进，从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
mul8bit_shift_add
- 移位相加8位乘法器，含有每个模块的详细说明-Shift and add 8-bit multiplier, and contains a detailed descr iption of each module
Multiplier
- 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
mux16
- 16位乘法器的verilog实现，可以通过仿真，采用的是移位的方法。-16-bit multiplier verilog achieve, through simulation, using the shift method.
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
multiplier-experiment
- 周立功Fusion StartKit，fpga开发板的实验例程，恒定系数乘法器实验-The ZLG Fusion StartKit, fpga development board test routines, the constant coefficient multiplier experiment
MULTI4BIT
- 4位乘法器由于所使用的软件是ISE，没有LPM_ROM可以直接调用，所以此设计直接调用的乘法器的IP核来完成此功能，达到同样的效果。-Four multiplier
mulbinarytree
- 16位二叉树乘法器（阵列乘法器），VHDL实现-16-bit binary tree multiplier (array multiplier), VHDL realization
multiply
- 本文利用全加器、半加器，利用进位保留的思想，在前向割集中加入四级流水实现了乘法器的设计，提高乘法器的运算速度，并且介绍了乘法器的VHDL的程序编写过程以及代码，并给出了仿真波形-In this paper, the use of the full adder, half adder using carry-save ideological forward cutset added four water to achieve a multiplier design, to improve the
ex2
- 加法器，乘法器，计数器，可实现加法，乘法，计数等功能-add，multi，counter，you could use it to achieve very many aims like the above
xiangwei_90
- 产生一组正交的载波信号，应用于斩波相乘控制，模拟乘法器-Generating a set of orthogonal carrier signals, multiplied by the applied chopper control, analog multiplier. . .
mul
- CCS环境下，在DSP硬件板上实现矩阵乘法器。-CCS environment matrix multiplier in DSP hardware board.
8mutip
- verilog 八位 乘法器-verilog eight multiplier