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VHDLsiweiquanjiaqqi
- 这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图的 请叫站长联系我
voterandcounter
- 用VHDL写的源代码程序,包涵三人表决器,七人表决器,全加器以及模24,模60的计数器,都是单文件的,由于程序小又多,所以集中在一起,供新学习VHDL语言的朋友们参考。
123654vhaing
- 八音自动播放电子琴设计 vhdl源码,文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play aut
1
- 基于eda中vhdl语言的一位全加器的设计,详细的设计过程和实验现象,相互学习-Based on EDA VHDL language in a full adder design, detailed design process and the experimental phenomena and learn from each other
1
- 1位全加器的vhdl设计 通过两个半加起实现-A full adder of VHDL design increases since the adoption of two and a half to achieve
Quartus7.2
- 通过VHDL实现4位全加器,8位全加器,和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
add_eight
- 用VHDL写的一个8位全加器的实验程序,供新手参考-Use VHDL to write an 8-bit full adder of the experimental procedures
binary_to_decima
- 8位全加器的VHDL描述,可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption,MAX+ plus Ⅱ can be used to run test
8WEIQUANJIAQI
- 8位全加器的VHDL语言描述,有需要的顶一下。-8-bit full adder described in the VHDL language, there is a need to click the top.
fadder
- 利用两个半加器来组成的全加器,是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language
myf_adder
- 用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL descr iption.
hadder
- 这是一个8位全加器,利用vhdl完成了电路的构成,-this is a 8 bit adder,
VHDL02
- 加法器和全加器参考程序,由VHDL代码编写。初学者可以看一看。内容无毒,下载请杀毒使用。-Adder reference procedures, prepared by the VHDL code. Beginners can take a look at. Content-free, download antivirus, please use.
fulladder4
- VHDL图形文件实现的4位全加器,希望对大家有用!-VHDL graphics files to achieve four full adder, in the hope that useful!
Full_adder
- 一种学习用的小程序,主要用与VHDL仿真的全加器的一段代码!大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie
f_adder
- 用VHDL语言写的全加器,比较简单-Written in VHDL language with the full-adder
EDA
- 课程实验,VHDL语言实现半加器全加器,频率计等,共四个-eda
Adder4
- 源码,内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder
Full_adder
- 全加器的VHDL逻辑编程,外加两个全功能,这个过程有些简单,但可能有一些初学者的帮助。-Full adder VHDL logic programming, plus two full-function, this process some simple, but there may be some beginners help.
full_aller
- 这是基于VHDL的一位全加器设计的程序,分析过程全面-This is based on a full adder VHDL design process, a comprehensive analysis process