搜索资源列表
cla20_n
- Verilog 20 bit的累加器 采用流水香设计,用5级4bit的超前进位加法器-Verilog 20 bit accumulator using water in Hong design, with five 4bit the look-ahead adder
jiafaqi
- 加法器是产生数的和的装置。加数和被加数为输入,和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入,而和数与进位为输出则为全加器。-Adder is generated and the number of devices. Addend and the summand input, and digital and carry the output device is a half adder. If the addend, the progress of summand bits
trans_sigPnoisePinterference
- 根据直扩原理,首先有随机数发生器产生一系列二进制信息数据(+1,-1),每个信息比特重复Lc次,Lc对应每个信息比特所包含的伪码片数,包含每一比特Lc次重复的序列与另一个随机数发生器产生的PN序列c(n)相乘。然后在该序列上叠加高斯白噪声和形式为i(n)=Acosw0n余弦干扰下次信号,切余弦干扰信号的振幅满足条件A<Lc。在解调器中进行与PN序列的互相关运算,并且将组成各信息比特的Lc个样本进行求和。加法器的输出送到判决器,将信号与门限值0进行比较,确定传送的数据为+1还是-1,计数器用
digital-adder-source-code
- FPGA的Altera Quartus II 利用汇编语言实现加法器数码管的现实程序源代码-The Altera Quartus II FPGA using assembly language to achieve the reality of digital adder source code
baweijiafaqi
- 八位加法器的VHDL程序,可以实现八位二进制数的相加。-Eight adder VHDL program that can achieve the sum of eight binary digits.
lab
- verilog语言设计同步加法器,异步减法器,16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
100vhdl
- VHDL100个例子,讲述VHDL基本应用,如加法器,移位寄存器等。-VHDL100 example, about VHDL basic applications, such as adders, shift registers.
TEST
- I2C总线的实现,一个基于计数器的加法器。其中使用三个寄存器来实现计数器的功能,再由两个半半加器实现全加器额功能。-realize the inter-integrated circuit bus
FPGASquare-RootRaised-CosineFilter
- 数字通信系统中, 基带信号的频谱一般较宽, 因此 传递前需对信号进行成形处理, 以改善其频谱特性,使 得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分-FPGA Implementation of Square Root Raised Cosine Pu
Adder
- VHDL语言设计的加法器,在试验箱上使用8个拨码开关设置要加的2个数,按键按下输出相加的结果,在试验箱上测试通过。-Adder VHDL language design, in the chamber using the DIP switch setting 8 to 2 to add the number of keys pressed result of the addition output of the chamber on the test.
Large-integer-large-integer
- 大整数加法器能够很方便地实现对大整数加法的快速运算-Large integer adder can easily achieve the rapid addition of large integer operations
eda
- 这是我们平时做的EDA实验,包括加法器,乘法器,以及状态机等-This is what we usually do the EDA experiments, including adders, multipliers, and the state machine, etc.
complement_adder
- 十六位补码加法器,输入为两个16位补码,输出和为17位补码,不虚溢出标志。-Sixteen complement adder, the input to complement the two 16-bit, output, and for the 17 complement, not virtual overflow flag.
adder_32bits
- 32位进位选择加法器,预置逻辑0和逻辑1,各模块并行运行,只要通过进位位选择逻辑0或者逻辑1即可,提高了运行速度。-32-bit carry select adder, preset logic 0 and logic 1, the modules run in parallel, as long as through the carry bit selection logic 0 or logic 1 can improve the speed.
jiajiajia
- VB加法器,可以进行加法运算,支持科学计数法以及小数等等。而已成为偷懒的好工具!-VB adder, addition operations can support scientific notation and decimal and so on. Only be a good tool for lazy!
summator
- 加法器是产生数的和的装置。常用作计算机算术逻辑部件,执行逻辑操作、移位与指令调用。在电子学中,加法器是一种数位电路,其可进行数字的加法计算。在现代的电脑中,加法器存在于算术逻辑单元之中。 加法器可以用来表示各种数值,如:BCD、加三码,主要的加法器是以二进制作运算。加法器可以用组合逻辑电路实现也可以用VHDL语言实现。-Adder is generated and the number of devices. Arithmetic logic unit is used as a computer
Adder_2bit
- 2位加法器,采用Verilog语言编写,在开发板上经过验证,希望对大家有所帮助-2-bit adder using the Verilog language, proven in the development board, we hope to help
cont60
- 六十进制加法器 可以实现六十位的技术功能-Six decimal adder can achieve the technical features sixty
DOSCalculator
- dos 加法器 实现先乘除后加减,先括号内再括号外的依次运算。-dos adder to achieve the first after the addition and subtraction multiplication and division, first in brackets followed by further operations outside the parentheses.
bcdfa
- 计算机组成原理,4位加法器实验VHDL代码。已运行成功。-Computer organization, 4-bit adder VHDL code experiments. Has been running successfully.