搜索资源列表
daima
- 2选一功能选择器！加法器，8选一等，一个个简单却很常用的单个模块！-2 Select a function selector! Adder, 8-to-first-class, a simple single module is very popular!
add16_32
- 十六位加法器，超前进位加法器，总共三十二位。 -Sixteen adder, look-ahead adder, a total of Thirty.
ad
- orcad 加法器 仿真电路 下载后 直接使用-orcad download adder circuit simulation directly using ~ ~ ~
adder
- 较好的加法器VHDL代码，大家需要可以下载，谢谢。-Better adder VHDL code, we need to download, thank you.
test
- 利用AT89S52开关控制由运放构成的加法器，实现输出电压是输入电压的0.1到1.5倍-Using AT89S52 switch constituted by the adder op amp, the output voltage is the input voltage of 0.1 to 1.5 times
4Verilog-HDL-
- 4位加法器的实现用于FPGA的开发环境 欢迎大家使用 非常感谢-4-bit adder to achieve a development environment for FPGA welcome to use thanks
Adder
- 简单加法器，实现了任意两个数的相加功能，有友好的功能界面，适合幼儿或小学生使用。-Simple adder
verilogfile
- 16位加法器，4位1组的超前进位加法器单独作为1个模块。-16-bit adder.
quartus
- 通过使用4位全加器和4位比较器以及相关组合逻辑的使用并结合BCD码加法规则构成4位BCD码加法器。-Through the use of four full adder and 4-bit comparator and associated logic of the use and combination with BCD adder rules constitute four BCD adder.
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
ADD
- 基于FPGA自带IP核建立的加法器，希望对大家有帮助！-FPGA-based IP core comes with the establishment of the adder, we want to help!
Prefix_KoggeStone_32
- 经典的kogge-stone加法器结构，32结构，verilog代码-Classic kogge-stone adder structure, 32 structure, verilog code
quanjiaqiheDchufaqi
- 设计一个全加器元件，再用该元件连成4位二进制加法器 设计一个D触发器元件，再用该元件连成4位寄存器 -Design a full adder component, then the component with a 4-bit binary adder design a D flip-flop element, then the components together into four registers
jiafaqi
- 改程序实现了简单的加法器功能，很容易完成加法运算。-Reform program to achieve a simple adder function, it is easy to complete the addition.
add
- 加法器的实现，用VHDL/FPGA/Verilog制作的实现的- adding machine use VHDL/FPGA/Verilog
add4
- 四位加法器verilog源代码，经过modelsim仿真验证正确，用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
yibanjiafaqidesheji-EDA
- 基于FPGA的快速加法器的设计与实现，在VHDL环境中波形图显示出结果，可以用二进制，十进制，十六进制表示 -FPGA-based fast adder design and implementation in VHDL environment, the results in the waveform display, you can use binary, decimal, hexadecimal
16-bit-adder
- 这是关于16位加法器的实现代码及仿真图形的压缩文档-This is about 16-bit adder implementation code and simulation graphics archive
dds1
- DDS设计原程序，子文件包含加法器，触发器，随机存储器等模块的设计，可简单实现仿真-DDS design of the original program, sub-file contains the adder, flip-flops, RAM, and other modules designed to achieve a simple simulation
butterfly1
- FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul