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add
- 在fpga上实现加法器功能，使用的是vhdl语言-Achieve sum functions on fpga
verilog
- 数字信号处理的FPGA实现 第三版 verliog 从简单的加法器 到 现代滤波器-FPGA implementation of digital signal processing third edition verliog from simple adder to modern filter
adder_4
- 三种设计模式的加法器，分别是行为及描述，串行模式，并行模式。希望对大家了解加法器有帮助-Adder three design models, and behavior were described, the serial mode, the parallel mode. I hope to help everyone understand adder
Verilog_100exaples
- Verilog的100个经典设计实例，包括交通灯的设计代码，智能时钟的设计代码，各种加法器。乘法器的设计代码-100 classic Verilog design examples, including the traffic light design code, intelligent clock design code, a variety of adder. Multiplier code
add8_shift
- n位可配置加法器,根据自己的配置扩展成n位加法器-n-bit adder can be configured to extend into the n-bit adder according to their configuration
adder
- 硬件实现的高速并行加法器，包括仿真使用的代码和case-high speed adder and test case
32ADD
- 32位超前进位加法器，verilog hdl代码实现，包含源程序-32 lookahead adder, verilog hdl code, including source code
8051_adder
- 8051单晶片加法器。结果可以通过4个LED 显示出来。 megawin的板子用于实现。-8051 adder. The results can be four LED display. megawin board for implementation.
add
- 用verilog实现的可综合的16位和32位加法器，经过验证了。-Implementation addition with verilog.
adder4
- 实现一个加法器功能，程序中添加一个加数和被加数，单击等号按钮即可得到加法结果。-Implement an adder function, program to add a addend and the augend, click the equal sign button addition results are obtaine
FinalDesign
- 实现逻辑门电路的绘制以及运算。并且实现了加法器、减法器、乘法器、比较器等运算-Implementation of logic gate drawing and operation. And implement the adder, subtracter, multiplier, comparator and other operations
adder
- 实现了简单的加法器，c++编程入门经典，程序更换了图标-Achieve a simple adder, c++ classic programming entry procedures to replace the icon
adder
- 自己做的几个不同方式实现的加法器的方法，可以参考一下-Adder several ways to do their own different ways, you can refer to
add4_bcd
- 程序描述了BCD码加法器，采用的是逢十进一的规则。-Procedures described BCD adder, using the rules of decimal.
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
square
- 用qt实现十进制加法器，对初学者来说是个不错的选择-Decimal adder with qt, for beginners is a good choice
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
jiafaqi
- 加法器运用vc++的mfc做的简单的加法器只能做加法。为了能下载~-Simple adder
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
four-lookahead-adder
- verilog_HDL-四位超前进位加法器,学习资料，可以方便的用-verilog_HDL-four lookahead adder, learning materials, you can easily use