搜索资源列表
BankerTest
- 银行家算法 随机生成资源种类 资源数 输出安全序列 检测安全状态-Banker' s algorithm randomly generated number of resources Resource type sequence detection output security security status
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
Verilog
- VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等-VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等
序列图像检测与提取
- 该文档提供了基于序列图像检测与提取的程序代码。
1111-Sequence-Detection
- 1111序列检测的设计VHDL代码，用状态机实现111序列检测的设计，如果检测到正确的序列，则led灯亮起，否则熄灭-1111 Sequence Detection design VHDL code, using the state machine to achieve 111 Sequence Detection design, if it detects the correct sequence, led lights, otherwise extinguished
SCHK
- 10位序列检测器，有序列产生，分频器，按键消抖，序列检测，数码管扫描等几个模块构成，设计天津工业大学课程设计-10 sequence detector with sequence generation, dividers, key debounce, sequence detection, digital scanning, and several other modules, curriculum design, Tianjin Polytechnic University
1
- 可输出中序遍历序列检测程序功能是否正确。如果每个分支节点用一个临时变量标记，则对四则运算表达式的抽象语法树进行后序遍历，可以得到输入表达式所对应的四元式序列（实验4要用到这样的四元式序列）-Preorder output sequence detection program functions correctly. If each branch node labeled with a temporary variable, then the abstract syntax tree arithm
cpc1
- 实现序列检测的功能，对特定数字序列成功的检测-Achieve the function of sequence detection for detecting the success of a particular sequence of numbers
Blind-semi-definite-sdp
- SIMO系统中4PAM_16QAM信号的半正定规划盲序列检测算法-Semi-definite programming sequence detection algorithm blind SIMO system 4PAM_16QAM signals
state
- 实现对输入序列检测功能 1． 低电平异步复位 2． 检测序列特征为10010 3． 输出高电平，维持一个时钟周期 4． 数据序列一个时钟周期为一个数据态，时钟上升沿触发检测 -Detection of the input sequence to achieve 1. Low asynchronous reset 2. Detection sequence is characterized by 10010 3. High output, maintainin
serial_number_check
- 序列检测，学习verilog三段式状态机的经典例程，modelsim仿真无误-Sequence Detection, three-state machine learning verilog classic routines, modelsim simulation is correct
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
vcPP6.0
- 背景差分法，帧间差分法,可以有效基于视频序列检测出动态目标，实现有效检测-Inter frame difference and background difference moving target detection phase fusion under the opencv platform based on vc++6.0
chenxu
- 序列检测其设计，检测11100110。并通过七段显示译码器显示。- Sequence Detection its design, testing 11100110.And through the seven-segment display decoder display.
VHDL-sequence-detector
- VHDL 序列检测 对特定的序列进行检测-VHDL sequence detector
xuljc
- FPGA编程，用Verilog语言实现序列检测功能-The FPGA programming, using Verilog language implementation sequence detection
cumulative-sums-test
- 01二值序列检测，进行简单的数值运算，并结合累加与检验算法-01 binary sequence detection, a simple numerical calculation, combined sum and test algorithms
06670125
- 本文提出了一种新的自动换合成孔径雷达（SAR）时间序列检测技术，即广义有序序列分析方法。-This paper presents a new automatic change de- tection technique for synthetic aperture radar (SAR) time se- ries, i.e., Method for generalIzed Means Ordered Series Analysis (MIMOSA). The method comp
xulie
- 序列检测，检测出序列11010后亮灯，文件是用verilog编写的-Sequence detection, after detecting a sequence of 11010 lighting, files are written with verilog