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digital_clock_design
- 利用VHDL语言，逻辑器件设计CPLD，实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
shuzishizhong125
- 数字钟的设计【数字电子技术课程设计】 数字钟实际上是一个对标准频率-The figure vies for the answering device by the subject circuit and expands the circuit to make up . Have priority in code circuit , latch , decipher circuit and export the input signal of the entrant team on the dis
shuzizhong
- 单片机学习的数字时钟设计，简单的数字钟源程序-Single-chip digital clock design study, a simple digital clock source
shuzizhong
- 带定时、调时功能的数字钟，用51开发，可作为课程设计的资料。-With timing, when the transfer function of digital clock, with 51 development, can be used as curriculum design information.
time
- 数字逻辑课程设计数字钟，用硬件描述语言完成，简单易懂。-Curriculum design, digital clock digital logic, using hardware descr iption language, complete, easy to understand.
shuizhongvhdl
- 这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
DigitalClock
- 此文件为SOC课程设计中数字钟的几个相关源代码-This file is the SOC course design digital clock source code for several related
shuzizhongcankaoverilog
- 这是我设计数字钟参考资料，还不错，适合初级verilog选手参考使用，一定得先看懂了一些设计，自己上手才会快。-This is my digital clock reference design, but also good for junior players for reference verilog, must first understand some of the design, their own will get started soon.
digitalclock
- 数字钟的VHDL设计 具有整点报时、闹钟等功能 -VHDL design of digital clock the whole point timekeeping, alarm clock and other functions
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
The_Final_Exp
- 嵌入式系统课程设计题目（2009年） 七段数码管数字钟（▲） 关键词：数字时钟 1、 硬件：JXARM9-2410教学实验箱，PC机。 2、 软件：PC机操作系统Windows（2000、XP）ADT IDE集成开发环境。 -Design of Embedded Systems Course Title (2009) seven-segment digital tube digital clock (▲) Keywords: digital clock 1, the hard
VerilogHDlclock
- 基于VerilogHDL设计的多功能数字钟-Based on the design of the multi-function digital clock VerilogHDL...
shuzizhong
- 多功能数字钟的设计，可显示时－分－秒、整点报时、小时和分钟可调等基本功能。-Multifunction digital clock designed to display- minutes- seconds, the whole point timekeeping, hours and minutes, adjustable and other basic functions.
VHDLshili
- 此内容为VHDL设计实例 一共有三个都是关于数字钟的功能要求的 但是没有说明 能看懂就行-The contents of VHDL design examples are a total of three functional requirements on the digital clock in but did not say can read on-line
8031
- 介绍了用8031 单片机控制的电脑数字钟的硬件结构与软件设计。给出了汇-Introduced the 8031 microcontroller using a computer controlled digital clock in the hardware structure and software design. Gives the Department of
LIBRARY
- 基于VHDL的数字钟的设计，能够显示年月日，时分秒等功能。-VHDL-based digital clock designed to display years on, when minutes and seconds functions
200971617402035228
- 数字钟的设计用到，数制、基本逻辑运算、逻辑门电路、组合逻辑电路、触发器、时序逻辑电路、脉冲的产生等数字电路知识。-Digital clock design used, number system, basic logic operations, logic gates, combinational logic circuits, flip-flops, sequential logic circuits, pulse generator and digital circuit knowledge
example1
- 采用nios2的嵌入式数字钟的设计与实现，首先使用quartus2中的sopc builder设计CPU内核，然后在nios2中庸C语言来实现数字钟的功能--Embedded digital clock with nios2 the design and implementation, the first to use quartus2 the sopc builder design CPU core, and then nios2 Mean C language function digita
MultifunctionDigitalClock
- 多功能数字钟的EDA设计研究，包含整点报时，计时，闹铃-Multifunction Digital Clock
project
- 介绍了利用VHDL硬件描述语言设计的简易数字钟的思路和技巧。在QuatusⅡ开发环境中编译和仿真了所设计的程序，并在可编程逻辑器件上下载验证。仿真和验证结果表明，该设计方法切实可行，具有一定的借鉴性。-digital clock