搜索资源列表
OOB_control
- 串行传输协议sata的物理层的控制模块的状态机-Serial transmission agreement of the physical layer control module sata the state machine.
FPGAFFT.rar
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计,FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
state_machine_watchdog.rar
- 基于状态机的CPLD/FPGA看门狗程序 难能可贵,State machine based on the CPLD/FPGA valuable watchdog process
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
SDRAM
- verilog语言对SDRAM读写时序的描述，采用状态机结构实现的读写功能-timing of the SDRAM read and write verilog language descr iption, a state machine structure to achieve read and write capabilities
uart
- 状态机实现的可配置uart模块，经过fpga验证-State machine implementation can be configured to uart module, after verification fpga
SimpleDES
- opnet和c联合编程，包括库文件、内核、状态机的代码，ppp的网络场景仿真代码。-Such as opnet and c joint programming, including libraries, the kernel, state machine code, the PPP s network scene simulation code.
pingpang
- FIFO读写，用使用状态机完成两片FIFO读写，乒乓操作。-FIFO read and write, using the state machine complete with two FIFO read and write, ping-pong operation.
MC9S12XS128
- 基于飞思卡尔S12单片机写的底层程序，基于状态机，可以非常简单的扩展操作界面。-Based on Freescale' s S12 MCU to write low-level program, based on state machine, the expansion can be very simple interface.
AD9833
- VHDL语言 状态机实现AD9833信号的产生-VHDL language state machine to achieve AD9833 signal generation
Drive-ADS8365-state-machine
- 驱动ADS8365状态机,Quartus II Verilog-Drive ADS8365 state machine, Quartus II Verilog
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
SDH
- SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
StateMachine
- 状态机的文档、状态机的例子程序和有关状态机的资料，通过文件可以了解labview状态机的原理和编程-The documents state machine, state machine examples of procedures and relevant information on the state machine, through the file labview state machines can understand the principles and programming
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
Senior-Advanced-FPGA-design
- FPGA设计高级进阶，讲述了流水线，乒乓操作，异步时钟域处理，状态机等内容-Senior Advanced FPGA design, about the line, ping-pong operation, asynchronous clock domain processing, state machine, etc.
74HC165Keyboard
- 74HC165N级级联键盘 状态机解码 -74HC165 keyboard state machine decoder
qep
- QP下的事件处理源码~基于状态机的实现~ -QP event handling source code under the state machine based on the realization of ~ ~ QP under the event handling source ~ based on state machine implementation ~
lpc
- LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
vhdl
- 自动打铃系统的VHDL设计中的状态机，自己已经检验过了完全正确-STATEMACHING OF AUTO RING WITH VHDL.