搜索资源列表
bcdadd
- 在matlab的simulink下建模实现bcd码的加法运算,其中使用了状态机。
Finit_state_machine_in_C
- C实现一个状态机,我做毕业设计,实现自组织网络,三个节点-Finit state machine implemented in C code
tlv5636
- 音频DA tlv5636的接口程序 经过硬件测试的成功 学习状态机对器件编程的经典-DA tlv5636 audio through the interface program to test the success of hardware 。state machine to study the classic programming device
mealy1
- mealy 状态机的独热编码源程序,接受么mealy状态机的编写规则。-mealy state machine of one-hot encoding source code, you mealy state machine to accept the preparation of the rules.
state
- 十种状态机例子,简单易懂,是学习fpga的好帮手-Dozens of examples of state machine, easy to understand, is a good helper fpga study
IIC_AD75
- I2C温度传感器ADT75的控制源码 使用verilog 状态机实现 易入门-I2C for ADT75 temperature sensor
SDRAMHDL
- SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation
VHDLexample
- 步进电机控制,直流电机控制,加法器,状态机等等经典的VHDL例子程序。-Stepper motor control, DC motor control, adders, state machines, etc. The classic example VHDL procedures.
chuanbingzhuanhuan
- 这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的,尤其在通信线路方面的复用和分解方面,原理上就是一个串并转换和并串转换的过程。举个简单的例子,计算机串口发送数据的过程,如果满足发送条件了,其实就是一个并串转换的过程了。好了,废话不说,看代码就是。 -And the string conversion of the code is relying on the synchronization state machine to achieve its c
jiaotongdeng
- 这程序是利用状态机来控制交通灯verilog码-This procedure is the use of state machine to control the traffic lights verilog code
liuVHDL
- 一种基于状态机设计的串并行转换电路,将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路, ADC的时钟由转换电路提供,-Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
state2
- 用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock
Multi-point_temperature_system
- 这是一个多点温度测量系统,通过三个传感器点采集温度,51单片机负责下位机的工作,然后通过RS232与PC机上的程序通信,在PC上可以查看这三路温度值,还能分别控制各路的开关状态,有温度超值报警等功能,-This is a multi-point temperature measurement system, through the acquisition of three-point temperature, single-chip 51-bit machine under the respon
parallelstatemachineinCS
- 在客户端和服务器架构中,平行状态机的使用,使用python实现的,最多可以有20个客户连接到服务器上,服务器将会验证客户端状态的改变-This demonstration illustrates the use of parallel statemachines in a client-server implementation.
Heilbronn_Visit_Design
- 海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述-Heilbronn Visit Design Digital Combination Lock
ADCINT
- 基于VHDL语言的A/D采样控制程序,程序采用状态机实现的-Based on the VHDL language, A/D sampling control procedures, procedures for the use of state machine to achieve the
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
moore
- 主要介绍moore状态机的详细功能及应用,程序是用hdl写的!-Moore state machines are introduced in detail the function and application of the procedure is written hdl!
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true