搜索资源列表
vhdl
- 通用寄存器，移位寄存器，简单状态机，直流电机控制器，-General registers, shift register, a simple state machine, DC motor controllers, etc.
vhdl1
- VHDL的几种状态机，双进程单进程以及其它类型。-Several VHDL state machine, dual-process single process, as well as other types.
electroniclock
- 1）能完成开锁功能 2）能实现设置密码的功能 3）用有限状态机的方法编程 4) 作业提交时间：在第14周周日前提交-1) to complete the unlock function 2) set a password to achieve the functions of 3) by the method of finite state machine programming 4) submitted the operating time: 14 weeks in the fir
EDA
- EDA实验讲义GK 包含GW48 EDA系统使用说明以及许多实例。比如有时钟使能的两位十进制计数器原理图输入设计、用状态机对ADC0809的采样控制电路实现、硬件电子琴电路设计-EDA experimental GK notes GW48 EDA system contains, as well as many examples of use. For example, there are two clock-enabled input decimal counter schematic des
telephone
- 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
SDRAMVerilogHDL
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
15AlteraIP
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
sequence_check
- 用状态机实现序列检测器的设计，并采用ROM结构输入待测序列进行仿真测试。-sequence inspector
HS100H_01
- 基于有限状态机的多级菜单，多义键盘监控源程序，含有点阵液晶驱动，串口通信等模块-Finite state machine based on multi-level menu, keyboard monitoring source polysemous, containing dot-matrix LCD driver, serial communications modules
state_bar
- 带同步复位的状态机,适用于VHDL语言操作,对于初学者或是深入的人都适宜-state bar
division
- 带同步复位的状态机,适用于VHDL语言操作,对于初学者或是深入的人都适宜-replacement_state_bar
HDB3_coder
- 实现了将64K低速NRZ码复接成2.048M高速HDB3码及其解复接过程，同时还用同步状态机剔除假同步和假失步的状态 -Achieved the 64K low-speed NRZ code 2.048M into high-speed multiplexing and demultiplexing HDB3 code then the process also removed using false synchronous state machine synchronization and f
stop_watch
- 使用状态机实现的秒表，另外包含计数器功能-The use of state machine to achieve the stopwatch
1
- VHDL语言在电路设计中的优化 vhdl语言，毛刺，状态机-VHDL language in the optimization of circuit design in vhdl language, burr, state machine
traffic
- 交通控制灯，状态机的方式现实，分为AB2个路口-Traffic control lights, realistic way state machine is divided into junctions AB2
123
- 基于quartus的，状态机实现流水灯，verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
viewxinhao
- 用labview开发的监控界面，下位机通过串口通讯向上位机发送数据，监控软件实时显示状态-Used to monitor the development of labview interface, the next bit plane up through the serial communication bit machine to send data, real-time monitoring software shows the status of
measure
- 用ＶＨＤＬ语言编写一个状态机电路，可实现对脉宽的测量-VHDL language with a state of electrical and mechanical way, enabling the measurement of the pulse width
FSM_Mealy
- 借助该MEAL状态机源码您就可以轻松设计自己需要的状态机-MEAL state machine with the source code you can easily design their own state machine needs