搜索资源列表
ADC0809_VHDL_QUAARTUSII_PROJECT
- FPGA模块工程、ADC0809状态机控制ADC0809_VHDL_QUAARTUSII_PROJECT可以直接使用！-FPGA module works, ADC0809 control state machine can be used directly ADC0809_VHDL_QUAARTUSII_PROJECT!
ADC0809_good
- 这是一个用VHDL编写的ADC0809的驱动程序，采用状态机的形式来写，很不错的-This is a VHDL prepared to use the ADC0809 driver, the form of state machine used to write very good
uart_Transmitter
- 自己写的一个uart驱动代码，是一个工程文件，适合初学者，里面的状态机的写法十分值得学习-To write a uart driver code, is a project file, suitable for beginners, which the wording of the state machine is worth learning
EDA
- 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器 内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
dui
- 这是一个利用MATLAB做的界面，用于上位机和下位机之间的通信，可以用于上位机控制下位机，同时可以采集下位机的运行状态并可以绘图，实时下位机状态变化反映变化-This is an interface to use MATLAB to do for the host computer and the next bit of communication between machines can be used under the control of upper-bit machine, can b
fsm
- 如何使用状态机综合电路，状态机大全等等，使用DC综合工具-How to use the integrated circuit state machine, state machine Guinness and so on, using integrated tools DC
key
- 非常好的AVR教程--基于状态机的键盘接口编程（CODEVISION编译器）-a very good AVR paper
fsm
- 高效的有限状态机，代码形式给给出 主要是我的一些学习资料-Efficient finite state machine, code form is mainly to give some of my learning materials
seqdet
- Verilog编写的有限状态机的程序，实现对一二进制序列的检测，该有限状态机提供8个状态的，可以任意修改，作为测试。-Verilog written procedures for finite state machines to achieve the detection of a binary sequence, the finite state machine with 8 states, and can be freely modified, as a test.
Automated_download_story_from_web_site
- 自动从小说网站抓取所有小说的源代码，包括html parser，ui。供从事相关工作的参考。c++写的。可以直接复用html parser的状态机。-Automatically crawl your site to all fiction novel, the source code, including html parser, ui. Engaged in related work for reference. c++ written. Can be directly reused html
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, mul
ctrller
- 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
PCI_VHDL
- 从PCI时序分析入手，重点阐述了PCI通用的状态机设计，说明了用VHDL语言来实现本PIC通信状态机的软件设计以及进行MaxPlusII验证的程序和方法。用该方法所设计的接口既可支持PCI常规传输，又可支持PCI猝发传输。-PCI timing analysis from the start, focusing on general-purpose PCI state machine design, described by VHDL language to achieve the PIC c
example2
- moore状态机程序 一共有四个状况，空闲 idle 等待 ready 信号准备好后进入判决状态 decision 否则继续等待 ready信号；判决状态 decision 中将 oe、we 信号置低，同时根据read_write 判定下一个状态是读状态 read 还是写状态 write；如果 read_write 为‘1’读状态 read，否则写状态write；读状态将oe 置高，we 置低；写状态将 oe 置低，we 置高。-moore state machine processes a
example9
- 用 epm240 驱动 adc0804 这个芯片,本实验用状态机来控制。-Epm240 Driver adc0804 with this chip, the state machine to control the experiment.
designrequirementbyvhdl
- 08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl
97288394finite_state_machines
- 状态机的描述,可以从简单到复杂,供初学者使用是很好的起步例子.-State machine descr iption, can be from simple to complex, for beginners to use is a good starting example.
EfficientSynthesizableFiniteStateMachineDesignusin
- 高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
AD0809
- verilog实现的“状态机实现AD0809数模转换”。-verilog to achieve a " state machine to achieve AD0809 digital to analog conversion."