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led
- 数字时钟,能够实现调节功能。用状态机实现扫描按键。是个不错数字时钟。-Digital clock adjustment function can be achieved. With the state machine to achieve scan button. Is a good digital clock.
VerilogSourceCode
- 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
keyboard
- AVR单片机基于状态机的矩阵键盘扫描，相当好-AVR microcontroller based state machine scans the matrix keyboard
xinjiaotong
- 自己编写的，使用Verilog语言辨析的在FPGA上实现的交通灯的红绿黄灯，用状态机实现，共有六种状态，红-绿、红-黄、左转弯、绿-红、黄-红、左转弯，每种状态配以数码管显示区分。-I have written, use the Verilog language Discrimination implemented in the FPGA, red, green and yellow traffic lights, a total of six states, red- green, red-
display_fsm
- 采用状态机移位显示字符的VHDL代码，包括QUARTUS2的完整工程。-Shifting display with state machine . VHDL code , including the complete QUARTUS2 project.
ModelingReactiveSystems
- 本书介绍了状态机的基本概念，并结合statemate开发软件详细阐述了基于状态机的嵌入式软件开发方法。该书的作者David Harel是UML中状态机的开创者，该书的重要性可见一斑。-This book introduces the basic concept of statemachine and details the development method using statemate software. David Harel, author of the book is the inv
zidongshouhuojisheji
- 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
SPconversion_CPLD_FPGA_VHDL
- 基于状态机的8bit并串变换，使用VHDL语言，使用Xilinx ISE，程序特点是使用了状态机，通过分析可以学习如何使用状态机编程，并完成8bit并串变换的功能-8bit based on state machines and string transformation, using VHDL language, using the Xilinx ISE, process characterized by the use of the state machine, the analysis c
mitfst-1.2.1
- 自动状态机的实现,可用来实现正则表达式的解析-Finite state transducer
demo100710
- 要点有3： 1. TMR1中断，每次中断显示led的一位，且将键盘的状态存储链推进一步。 2. TMR1中断处理中，为便利实现各位的显示，采用了寄存器4(FSR)间接寻址方式。 3. 键盘用多级状态机方式，不会为按键判断占用机时，整体显示和键盘响应非常“干脆”；用“下键”标志防止重复读键，从而对于下键和抬键的开关抖动都能够有效抑制。-Main points of 3: 1. TMR1 interrupt, each led one of the interrupt displa
file
- 单片机多级菜单编程使用状态机不知道对不对请指教-Microcontroller programming using multi-level menu, the state machine does not know right Please advice
status_pt-1.4
- 使用状态机实现的小型任务调度程序，非常强大，我使用这个做产品已经1年多的时间了，很稳定。-Using the state machine to achieve a small task scheduler, very powerful, do I use this product has a more than a year, and very stable.
E1
- 分析帧同步算法，提供帧同步的状态机实现图以及得到的正确仿真图形。-Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics.
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
state_machine
- 摩尔状态机的程序，超经典的，用VHDL写的，初学者可以参考-Moore state machine program, ultra classic, written with VHDL, beginners can refer to
FsmTutorial_V1
- 用FSM工具进行状态机开发的教程，包你一看就会-State machine with the FSM tool development tutorial, including a look you' ll
DAstate
- 状态机，用FPGA控制DA发送串行指令方案-State machine, with the FPGA to send the serial command control program of DA
XLXH
- 完成序列为0111010011011010的序列生成器 2．用状态机设计实现串行序列11010的检测器 3. 若检测到符合要求的序列，则输出显示位为“1”，否则为“0” 4. 可对检测到的次数计数 -Complete sequence is 0111010011011010 sequence generator 2. State machine design using serial sequence of 11 010 detector 3. If the sequence i
1324135132324
- FPGA嵌入式编程，利用状态机实现AD转换功能，内附程序-FPGA embedded programming, using the state machine to achieve AD conversion function, enclosing the process
vhdl2
- vhdl设计实例二：测试向量级波形产生，状态机实例-vhdl Design Example Two: Testing the order of waveform generation, the state machine instance