搜索资源列表
double_subc
- Verilog 下 16位除法算法程序,高精度,固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
div
- 利用Verilog实现定点数的除法,在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve
jianfa
- 用verilog编写的用减法实现除法功能-Prepared using verilog function to perform division by subtraction
div_verilog
- 基于二进制移位用verilog实现除法的两种方法-Shift based on the binary division with verilog two methods to achieve
divide
- divide模块,实现除法功能。该module是用Verilog编写的,压缩包里包括了设计程序以及测试程序(testbench)。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
Division
- Verilog hdl 除法综合仿真实现,另包含测试文件-Verilog hdl Division
DataCycle
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineSim
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PIPELINE
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PipelineCPU
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
divider
- verilog 实现的除法运算器,可以进行修改。实现更多位宽的数据。-verilog implementation of division operation can be modified. Achieve more wide data.
mydiv
- 实现除法运算的Verilog实现(累加比较法)-The division operation Verilog achieve (cumulative Comparative Law)
div
- 两个3位二进制数的除法,结果(整数商)输出到数码管显示-verilog multply
add_tree
- 加法树的源代码,是乘法和除法的基础,也即数字电路的verilog基础代码,已经仿真过,完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
div
- FPGA的IP核中除法算法的源代码,是Verilog语言的,易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
divide
- 用veriog实现的任意位数的除法,在modelism中验证过了已经。-Implementation division with verilog.
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器,除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
FPGAcode
- verilog HDL语言编程实现比较、分频、除法、阻塞与非阻塞语句的源文件和test文件-compare, division,half_clock,block and unblock
Frequence-Test
- 基于FPGA的数字测频电路(307.617KHz),verilog文件。分频模块,循环移位除法模块,测频模块。- U57FA u4E8EFPGA u7684 u6570 u5B57 u6D4B u9891 u7535 u8DEF uFF08307.617KHz uFF09 uFF0Cverilog u6587 u4EF6 u3002 u5206 u9891 u6A21 u5757 uFF0C u5FAA u73AF u79FB u4F4D u9