搜索资源列表
EDAkechengsheji
- 实现6位频率计,防止数据溢出,并对频率进行三分频-Frequency to achieve 6 to prevent data overflow, and one-third of the frequency band
efcount
- 完整的等精度频率相位计,包含了项目文件、VHDL源代码、RTL电路图-Such as the complete phase of the frequency accuracy, including the project document, VHDL source code, RTL circuit
fequency
- 基于CPLD的等精度数度频率计,可以通过外设功能按键实现,频率、相位、占空比等参数的测量。-CPLD based on the number of degrees of accuracy, such as frequency meter, key peripheral functions can be achieved, frequency, phase, duty cycle measurement of parameters such as
cepin
- 基于等精度测频法的频率计测频模块,用VHDL 编写,在QUARTUS里面编译成功的-Such as precision frequency measurement method based on the frequency meter measuring frequency module, using VHDL written inside the compilation of success in the QUARTUS
main
- 交通信号灯 原代码 西安交通大学 电信学院 FPGA设计课下作业-Traffic lights of the original source, Xi' an Jiaotong University School of FPGA design course telecommunication operating under the
vhdl
- 用vhdl实现频率计,提出一种用vhdl实现的等精度测频率系统设计。-Frequency counter using vhdl implementation is presented using vhdl achieve precision measurements such as frequency of system design.
D
- VHDL数字频率计(1)频率测量范围: 10 ~ 9999Hz 。 (2)输入电压幅度 >300mV 。 (3)输入信号波形:任意周期信号。 (4)显示位数: 4 位。 (5)电源: 220V 、 50Hz -vhdl
Digitalfrequency
- 数字频率计VHDL程序与仿真,附有仿真截图和源程序注释-Digital frequency meter VHDL procedures and simulation, with simulation screenshots and source code comments
plj
- 这是一个频率计的源代码,用的是VHDL语言设计的,能够测量0-20KHZ的频率!-This is a frequency meter of the source code, using the VHDL language design, can measure 0-20KHZ frequency!
plj
- 数字频率计 在1秒内对被测信号进行计数,并将数据送至控制器,控制器根据数据自动选档,量程分为0--10KHz 、10KHz --100KHz 、100KHz --1MHz 三档。 数据采用记忆显示方式,即计数过程中不显示数据,待计数过程结束以后,显示计数结果,并将此显示结果保持到下一次计数结束。-Digital frequency meter in 1 second count of the measured signals and data sent to the controller
counter_bcd7
- bcd十进制计数器,用于频率计设计的计数器单元,输出zeros用于选通量程使用!-bcd decimal counter, the counter for frequency counter design unit, the output zeros for the use of strobe range!
aa
- 数字频率计VHDL程序-Digital frequency meter VHDL program
PinLvJiShuQi
- 数字频率计VHDL程序与仿真 功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的 --高4位进行动态显示。小数点表示是千位,即KHz。 --最后修改日期:2009.4.9。-frequency counter
VHDL-djdplj
- 基于VHDL语言的十进制等精度频率计的设计,采用VHDL语言,运用自顶向下的设计思想, 将系统按功能逐层分割的层次化设计方法,使用Quartus8.0开发环境,实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by func
4-10-VHDL-f1
- 四位10进制VHDL频率计设计说明 四位频率计的结构包括一个测频率控制信号发生器、四个十进制计数器和一个十六位锁存器(本例中所测频率超过测频范围时有警示灯)。-Four 10-digit frequency counter VHDL design descr iption of the structure of the four frequency meter includes a measuring frequency control signal generator, four deci
plj
- 此程序为fpga的频率计vhdl程序,功能是可以检测到输入信号的频率并且通过八位数码管显示-This procedure is the frequency counter vhdl fpga program function is to detect the frequency of the input signal and the digital display by eight
VHDL-based-digital-frequency-meter-
- 本源码介绍了基于VHDL的数字频率计设计,其风格简约而实用-The source describes the VHDL-based digital frequency meter design, the style is simple and practical
pinlvji
- 自己编的一个频率计,verilog语言写的,用数码管显示方波的频率,测量量程是0.1hz~9999999hz,测方波的稳定性极高。-Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square w
vhdl
- 交通灯控制 频率计case when语句 vhdl硬件描述语言编写-Vhdl traffic light control hardware descr iption language of transformation to achieve control of traffic lights