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TLC549
- TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础而构造的CMOS A/D转换器。它们设 计成能通过3态数据输出和模拟输入与微处理器或外围设备串行接口。TLC548和TLC549仅用输入/输出时 钟（I/O CLOCK） 和芯片选择（CS） 输入作数据控制。TLC548的最高I/O CLOCK输入频率为2.048MHz， 而TLC549的I/O CLOCK输入频率最高可达1.1MHz。 有关与大多数通用微处理器接口的详细资料已由工厂 准备好，可供使用。-TLC5
fequency
- 用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）-VHDL language used to describe the project examples Cymometer (quartus 7.2 at the use of)
123456
- 很不容易找到的资料，基于VHDL的频率计设计 希望有用-Not easy to find information on the frequency meter based on the VHDL design seek to help
digital_frequencycounter
- 一个简易的数字频率计，可以对一个输入的信号频率进行测量并显示输出，适合VHDL的初学者-A simple digital frequency meter, you can enter the signal of a frequency measurement and display output, suitable for beginners VHDL
f_cout
- 基于Quartus II的8位十六进制频率计的项目设计，包含了项目文件和VHDL源代码-Quartus II-based 8-bit hexadecimal frequency of project design, including project documents and VHDL source code
djsz
- 此为等精度数字频率计的设计，用单片机汇编语言和VHDL语言实现准确的频率采集功能。-This is the digital frequency meter accuracy, such as the design, with single-chip assembly language and VHDL language features accurately the frequency of collection.
digitalfrequencymeter
- 介绍了基于VHDL开发的数字频率计 从方案到结果-digital frequency meter
cymometer6b
- 一个基于alter的FPGA开发的，实用完整的6位十进制频率计。-6-bit cymometer realized by vhdl,it is useful very much.It has been tested and can be used with any change.
EDA
- 一个关于八位十六进制频率计设计的VHDL语言编程 可以下载的哦-a good word about EDA you can get some information from it
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
freqtest
- 用VHDL编写频率计，包含QUARTERSII的仿真，很好学习-The preparation of the frequency of use of VHDL, including QUARTERSII of simulation, a very good learning
frecount
- 基于vhdl的频率计控制器模块设计，已经经过调试，可直接调用-Vhdl based on the frequency of the controller module design, debugging has been directly call
FREQ
- 硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Descr iption Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
Project_of_DDS
- 基于VHDL硬件描述语言的数字频率计设计-Project_of_DDS
FREQTEST.tar
- VHDL写的16进制显示数字频率计，用8位数码管显示-16 hexadecimal display digital frequency meter VHDL
EDA
- 课程实验，VHDL语言实现半加器全加器，频率计等，共四个-eda
div_freq
- 一个数字频率计。利用VHDL实现。有3个VHDL文件组成。其中div_fre为顶层文件-A digital frequency meter. Use of VHDL implementation. There are three VHDL files. One of the top-level document div_fre
frequency_counter
- 数字频率计的FPGA设计与仿真，VHDL版本，适合初学-Digital frequency meter for FPGA Design and Simulation, VHDL version, suitable for beginners
Frequency_Counter
- 基于ep3c25的FPGA频率计的简单设计（用VHDL编写），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using VHDL written), directly open a can ... ...
freq
- 应用VHDL语言设计低频数字频率计，选择测频法方案，主要是控制电路，由其产生闸门、清零和锁存等信号。-VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.