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std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
Modulo.vhd
- modulo 2 adder using for some DSP applications
grlib
- gaisler lib. Format .vhd
usb.vhd
- 用FPGA模拟USB功能，采用VHDL语言编写，代码完善编译通过-USB functionality using FPGA simulation using VHDL language, compile the code complete
simpleLed.vhd
- LED BLINK TEST for FPGA
delay
- 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
VHD
- RS编码中用到的交织和去交织程序，VHDL描述，交织深度8-nterlace with VHDL，depth is 8
freqtest_dec
- 用VHDL设计了一个频率计，给出了各模块的详细源码，并给出了注解，对初学者及课程设计有帮助。-VHD designed with a frequency counter, gives the details of each module source code, and gives notes on programs designed for beginners and helpful.
color_converter_latest.tar
- The main purpose of the core is a color transform tasks such as CIE XYZ<->RGB, different RGB<->RGB and RGB<->YCbCr operations. The main part of color conversions from one to another color system concludes in 3x3 matrix multiplicatio
chufaqi
- 四位除法器：使用vhd实现四位的有符号除法器-Four division: Use vhd signed to achieve four of the divider
FPGA_parallel_serial_conversion
- FPGA的并行串行转换实例，两个.vhd文件-FPGA parallel serial conversion instance, two. Vhd files
bin2bcd
- 用来将二进制的信号转化成BCD码形式的信号，用来在数码管上显示相应的数字。-To the binary signal into BCD code in the form of signals, used in the digital display the corresponding number.
VHDLSaler
- 文件名：pl_auto1.vhd。 --功能：货物信息存储，进程控制，硬币处理，余额计算，显示等功能。 --说明：显示的钱数coin的 以5角为单位。-library ieee use ieee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic
URAT_VHDL_procedures_and_simulation
- URAT VHDL程序与仿真。 1. 顶层程序与仿真 （1）顶层程序 --文件名：top.vhd。 --功能：顶层映射。 --最后修改日期：2004.3.24。-URAT VHDL procedures and simulation. 1. Top-level program and Simulation (1) top-level program- the file name: top.vhd.- Features: top-level mapping.- Last mod
VHDL
- VHDL數字控制系統設計範例所有章節的VHD範例源碼-VHDL digital control system design examples for all sections of the sample source VHD
lcd_driver_projectComplete
- LCD CONTROLLER -- File name : lcd_driver.vhd -- -- Project : EE367 - Logic Design (Spring 2007) -- LCD Driver -- -- Descr iption : VHDL model LCD Controller Using State Machines -- -- Author(s) : Clint Gauer -- Montana State Univers
QuartusII_shuoming
- QuartusII简易操作说明 VHDL 仿真器 利用Quartus II 产生.VHO 和.SDO利用在sim_lib 目录中的APEX20K_ATOMs.VHD 和 APEX20K_COMPONENTS.VHD 文件 Verilog 仿真器 -QuartusII VHDL simulator simple instructions generated by Quartus II. VHO and. SDO use in sim_lib directory APEX20K_
BtoGray.vhd
- Binary to gray converter in VHDL
clock_divider.vhd
- A generic clock divider described in VHDL language