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6soft_247MHz_channel
- lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟
cnt10.vhd
- 设计一个10进制同步计数器，带一个清零端，一个进位输出端。（如果改成六进制，应该如何修改程序） 计数器分为同步计数器和异步计数器两种，是典型的时序电路，分析计数器就能更好的了解时序电路的特性。所谓同步计数器，就是在时钟脉冲的控制下，构成计数器的各触发器同时发生变化的那一类计数器。异步计数器又称行波计数器，它的下一位计数器的输出作为上一位计数器的时钟信号，这样一级一级串接起来就构成了一个异步计数器。异步计数器与同步计数器不同之处就在于时钟脉冲的提供方式，但是，由于异步计数器采用行波计数，从
VHD
- 此为基于Xilinx的FPGA用VHDL实现的FIFO，已调通，可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
CONTROLLER.vhd
- Controller source code for double data rate sdram1
SIGNAL-GENERATION.vhd
- Signal generation for double data rate
INIT-AND-CMD-FSM.vhd
- INItialization and command for double data rate
TEST-BENCH.vhd
- test bench for ddr 1
DATA-PATH.vhd
- signal data for ddr sdram
Binary_Multiplier_Binary_Multiplier1.vhd
- its vhdl proggrame for binary multiplication
qww
- DAC0832 接口电路程序，这都是源程序，如果有需要用VHD的文件可联系我-DAC0832 interface circuit procedure, this is the source, if there is a need to use the VHD file can contact me
lfsr
- lfsr.vhd - The top module in the project. lfsr_pkg.vhd - The package file used for supporting the lfsr top module. lfsr_tb - A testbench code for lfsr module. manual.pdf - A short documentation on this project. README.txt - A short descr i
JKF.vhd
- pulse framing circuit
servomat
- antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "ser
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
74ls160
- 这是一个使用vhdl语言编写的74LS160计数器，具有同步置位，异步清零的功能。-This is a use vhdl language 74LS160 counter with synchronous set, asynchronous clear function.
traffic_light
- traffic_light VHD交通灯控制-traffic_light(control) (Entity and Architectures)
7z922
- 7-zip是个文件压缩解压程序，支持7z, XZ, BZIP2, GZIP, TAR, ZIP, WIM, ARJ, CAB, CHM, CPIO, CramFS, DEB, DMG, FAT, HFS, ISO, LZH, LZMA, MBR, MSI, NSIS, NTFS, RAR, RPM, SquashFS, UDF, VHD, WIM, XAR-7-Zip is a file archiver with the high compression ratio. The program
TD1_11
- add soubstraction td 1 VHD L SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ-add soubstraction td 1 VHD VHDL SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ
spi_cpld_vhdl
- The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of S
smartcard_vhdl
- Readme File for Smart Card Reader File Contents ************************************************************************* This zip file contains the following files: -- VHDL Source Files in Smartcard: Top.vhd - top level file for Pic