搜索资源列表
95637012Multiplier
- 一种可以完成16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法,简化了部分积的符号扩展,采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元,整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
Multiplied-by-large-Numbers
- 汇编 大数相乘 include irvine32.inc value3=value1*value2 .data str1 byte "请输入16进制的32位整数(乘数)(8个):",0 str2 byte "请输入16进制的32位整数(被乘数)(8个):",0 str3 byte "相乘结果为:",0 value1 dword ? 乘数 value2 dword ? 被乘数 value3 dword 2 dup(0) 结果 m dword 0 用m
5-6
- 用verilog实现节省乘法器的16位复数乘法-16-bit complex multiplication verilog to achieve savings multiplier
Ex3_4
- 两个16位整数相乘,乘积总是“向左增长”,这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器,就要开销2个机器周期以及2个字的程序和RAM单元;并且,由于乘法器都是16位相乘,因此很难在后续的递推运算中,将32位乘积作为乘法器的输入。然而,小数相乘,乘积总是“向右增长”,这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下,既可以存储32位乘积,也可以存储高16位乘积,这就允许用较少的资源保存结果,也便于用于递推运算中。这就是为什么定点DSP芯
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器,可以输入两个8位数据,出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
mul16
- 16位二进制数移位乘法器的实现,使用Verilog HDL实现-The realization of the 16 bit binary number shifting multiplier, use Verilog HDL to implement
16x16multiplier
- Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only
mux_16bit_sign
- 16位有符号和无符号乘法器FPGA源代码-16-bit signed and unsigned multiplier FPGA source code
booth
- 16位booth乘法器的实现:先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中,由最低位与虚拟位开始,一次判定两位,会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, startin
original_code_multiplier
- 16位原码乘法器,附带测试程序,实现两个16位的乘数相乘。(16-bit original code multiplier with test program)