搜索资源列表
amba3core.rar
- amba3 sva 完全验证的代码，有verilog的和systemverilog的,amba3 sva fully validate the code, and the Verilog and SystemVerilog
AN151
- AMBA Application Note: AN151 - Using EB with example AXI Logic Tile. -AMBA Application Note: AN151- Using EB with example AXI Logic Tile. This example shows how to use the EB baseboard with an example AXI Logic Tile. The following board c
AMBAaxi
- This AMBA® AXI Protocol v1.0 Specification-This is AMBA® AXI Protocol v1.0 Specification
AxiPC
- fpga axi测试程序,可测试符合axi协议的ip核-fpga AXI4 TEST routine，can be used to test ip which is in amba.
IHI0022D_amba_axi_protocol_spec
- this a standard of AMBA about AXI 4-lit and AXI-this is a standard of AMBA about AXI 4-lit and AXI
AMBA_AHB.rar
- amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
merged_document
- report of amba axi.Also icludes samples
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
shruthi-proj
- The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high
AMBA_v30_AXI_v10
- ARM AMBA AXI Protocol guide
AMBA_AXI-bus
- ARM AMBA AXI总线原理分析，详细说明了AXI总线原理；-ARM AMBA AXI bus details, details the AXI bus principle
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
arm_amba_reference_manual.tar
- ARM AMBA REFERENCE MANUAL! 2011 YEAR
AXI4与AXI3的区别
- AXI4与AXI3的区别,l例如：AXI4对burst length进行了扩展：AXI3最大burst length是16 beats,而AXI4支持最大到256 beats，但是仅支持INCR burst type超过16 beats，exclusive access也不能超过16beats;。(the different of AXI4 and AXI3)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)