搜索资源列表
pipeline
- 用Quartus II 设计的3级流水CPU,指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
cpudesign
- Risc 32位CPU设计方法,由牛人主讲,可以好好学习-Risc 32 Wei CPU design methodology, from the cattle were speakers, you can learn
ppc8260-design
- powerpc cpu mpc8260 参考设计,总线为60x-compatible-powerpc cpu mpc8260 reference design
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
cpu_16bit
- design cpu 16 bits by verilog HDL.
VHDLmipsPipeline
- 32 位MIP流水线CPU设计,5 stage,代码详细,包括ALU,存储器,寄存器等,是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
wenduyalicaijixitong
- 设计的为一个温度压力实时采集显示系统,其具体如下:(包括源码) 1.以MC51单片机为CPU设计系统 2.每5分钟采集一次温度信号,10分钟采集一次压力信号。并实时显示温度、压力值。 3.比较温度、压力的采集值和设定值,控制升温、降温及升压、降压时间,使温度、压力为一恒值。 4.设温度范围为:-10~+40摄氏度、压力范围为0~100pa;升温、降温时间和温度上升、下降的比例为1摄氏度/分,升压、降压时间和压力上升、下降的比例为10pa/分钟。 -Design tempe
top
- 简单cpu设计 -包括内存单元,运算单元,数据及模块同步单元,状态机单元-CPU design- include memory module, alu module, synchronization module(data and block), finite state machine module
CPU
- 介绍如何运用VHDL设计CPU。并且简单介绍了CPU的内部结构与功能-Describes how to use VHDL design CPU. And a brief introduction of the CPU' s internal structure and function
cpu_1
- mips单周期cpu设计,实现MIPS中的11条指令,在设计的cpu中运行快速排序程序进行验证。-mips one cycle cpu design,run quick sort promgram for test.
MultiCLKCPU
- 本设计实现了多周期CPU的设计,运行环境是quatrus2;该多周期CPU可以处理22条32位指令(具体指令见源码,绝不坑人)。压缩包内含有源代码,程序模块表和实验报告以及详细的设计图,是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令,解决了大部分数据相关,结构相关,乘除法的流水化处理等问题,并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
dcv
- 一种实用的单片机双CPU设计方案及其应用-A practical single chip dual CPU design and its application
8bitRISCCPU
- 该文件是8位CPU设计硬件描述语言,对于初学者来说可以作为参考-The file is 8-bit CPU design hardware descr iption language can be used as reference for beginners
NonPipelined_Design
- 用VHDL实现的非流水线CPU设计,可以稍加改动变成流水线设计-VHDL implementation with non-pipelined CPU design
Structure_Design_of_Drgon2E
- 国产CPU龙芯2E设计方面的说明文档,是编程以及CPU设计和学习的理想材料-Domestic Godson 2E CPU design documentation, programming and CPU design and is ideal for learning materials
CPU-heat-sink-and-thermal-analysis-of-structural-d
- CPU散热器结构设计与热分析,对于做机械设计的朋友应该有一定的参考作用!-CPU heat sink and thermal analysis of structural design, mechanical design for a friend so there should be some reference!
Digital.Logic.And.Microprocessor.Design.With.VHDL.
- 设计数字电路和CPU的教程,使用VHDL语言。国外牛人写的书,很强大,很详细,英文原版电子书。-Digital.Logic.And.Microprocessor.Design.With.VHDL
VerilogHDLexample
- 可综合的VerilogHDL设计实例 ---简化的RISC CPU设计简介-VerilogHDL comprehensive design example can be simplified RISC CPU design--- Introduction---
cpu16
- 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code