搜索资源列表
I2c-design-basedNios-II-
- 基于FPGA的NIos II嵌入式系统通过I2C总线协议对串行电可擦写可编程只读存储器（AT24C02）进行读写操作，通过串口调试工具查看数据的传输是否正确。-NIos II FPGA-based embedded systems through the I2C bus protocol on the serial electrically EPROM (AT24C02) read and write operations, through the serial port debugging t
UartRecv
- FPGA Verilog HDL 语言构建串口接收器的详细方案设计-FPGA Verilog HDL language construct serial receive a detailed program design
UartSend
- FPGA Verilog HDL 语言构建串口数据发送器的详细方案设计-FPGA Verilog HDL language construct serial data transmitter detailed program design
UltraSensor-Vram-V8
- Verilog语言编写的FPGA程序，有串口收发引擎代码，AD初始化采集代码,键盘扫描代码-FPGA Verilog language program, a serial port transceiver engine code, AD initialization acquisition code, the keyboard scan codes
FPGA_SAA7113
- 飞利浦SAA7113的串口控制程序，基于FPGA的，使用VHD语言。-Philips SAA7113 serial control procedures, based on FPGA, using VHD language.
10_ps2_keyboard_test
- FPGA通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。 实验时，需要接键盘，还要用调试助手，下载程序后，在键盘上按下一个键，比如A，则在PC调试助手上可看到A -Through FPGA receive the ps2 keyboard data, and then receive the letters from A to Z key value into corresponding ASII code, through A seri
Serial_port_modul
- 串口通讯的Verilog程序，用于FPGA控制串口进行数据发送，接收，包含一个串口模块和一个进行调试的主控模块，主控模块可以随意自我设置，串口模块是固定的，全部程序都经过调试，都带有注释，很清晰。-Verilog serial communication program for FPGA control serial data to send, receive, including a serial debugging module and a control module, control m
09_uart2
- PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示-Open on the PC serial debugging assistant, send a character to the development board (the middle line connected through the serial port) FPGA received character, sent back to the PC, is d
UART
- FPGA实现串口的收发，可以改波特率。Verilog HDL语言-FPGA Verilog HDL
FPGA_UART
- FPGA实现UART串口通信协议 采用VHDL语言，顶层文件采用原理图的方式，简洁直观-FPGA Implementation of UART serial communication protocol
UART
- 用verilog编写的UART串口通信程序，经验证误码率为0，系统由ARM控制FPGA的串口进行通信；-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
UART_VERILOG
- 该程序实现在ALTERA FPGA 上使用VERILOG HDL语言实现串口通信。-The program in ALTERA FPGA VERILOG HDL language used on serial communication.
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
RS422_receive
- 该代码为串口接收数据源程序，可以帮助理解FPGA接收串口数据原理-UART RS422 receive
UART
- 实现了FPGA和PC之间通过串口相互通信-Achieve a FPGA and PC via the serial port to communicate with each
EXP42_RS232_PIANO
- 在EP3C5E上进行试验，PC机检测到PS2键盘，将键盘的数值通过串口传输给fpga，fpga驱动蜂鸣器发出音乐。-Tested on the EP3C5E, PC machine detects the PS2 keyboard, the keyboard' s numeric via the serial transmission to the fpga, fpga drive buzzer music.
EP2C8-2010_FPGA
- EP2C208C8 FPGA开发源代码（芯蓝C8板） turn_on_led 点亮LED sw_led 拨动开关控制LED rider_led 跑马灯 water_led 流水灯 key_led_without_debounce 轻触开关控制LED，无按键去抖 key_led_with_debounce 轻触开关控制LED，有按键去抖 seg7x8_dynamic_disp 七段数码管动态显示 matrixKeyb
VHDLRS232Slave
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 //制器，10个bit是1位起始位，8个数据位，1个结束 //位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 //现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是 //9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 //划分为8个时隙以
uart_serial_vhdl
- fpga例程：用实fpga现uart串口通讯的vhdl详细代码，附一个串口通讯助手小插件-fpga routines: solid fpga vhdl now uart serial communication code in detail, with a small plug-in serial communications assistant
I2C_i2c
- fpga例程：用fpga实现i2c串口通讯的vhdl详细代码，完整的quartus工程，可直接用-fpga routines: i2c serial communication with fpga implementation details of vhdl code, complete quartus project, can be directly used