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20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯,包括68013的固件以及fpga的代码(verilog)。摸了好久才调试通过的,特共享出来解救苍生!-fx2lp 68013 xilinx XC3s400 slave fifo
FPGA2-DSP2-EDMA
- 例程是FPGA通过EMIF给DSP发送数据,里面包含了一个简单的状态机和一个基于IP核的fifo,适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners
YJ_EP4
- 与Cpress CY8013所对应的 FPGA端的开发 使用NIOSII NIOSII 连续往USB FIFO 端点里灌数据 上位机不断的接收 陪和我的上位程序可以达到30Mbyte/s 需要上位机程序的去搜索TestUSBSpeedMFCNovember -upload-And Cpress CY8013 corresponding end FPGA development using NIOSII NIOSII continuous irrigation to USB FIFO
uart_fifo
- 带fifo的串口通信verilog设计,该设计为学习uart所用,完成PC端发送至fpga后fpga原数据返回,支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
wishbone
- Wishbone规范具有如下特点:简单、紧凑,需要很少的逻辑门 完整的普通数据据传输总线协议,包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian),接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议,允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
syn_fifo
- 关于FPGA同步FIFO和异步FIFO的编写和设计方案-Writing and design on FPGA synchronous and asynchronous FIFO FIFO
FPGA_Project_Files
- 此例为FPGA发送数据包到pci9054,用到fifo模块,还有sram模块,比较复杂。应用在pci9054与fpga通讯-This example sends the packet to the FPGA pci9054, use fifo module, as well as sram module, is more complex. Application pci9054 communication with fpga
FPGAluojidaima
- 16通道逻辑分析仪,100M,FPGA代码,包括FIFO,dram,usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码,里面包含所有的fifo,状态机源代码,drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio
spi_cbb
- 基于FPGA设计,verilog语言变成的,SPI通用接口模块,顶层已封装成类似标准的FIFO接口;提供仿真文件;仿真器为modelsim10.0c,波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计,大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF(q)乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
local-bus
- 基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。-FPGA-based local bus interface. Based fifo contains two programs and the general register.
FPGA_emif
- 接口模块,通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块,每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器,寄存器功能可自定义。模块还包含两个全局寄存器,可实现全局复位,中断等功能。该模块以应用于实际的项目中,目前运行良好-FPGA to emif
fifo_1
- 本程序是基于Xilinx的FPGA简单代码编写,对fifo的ip核进行简单的配置,并通过仿真代码进行仿真观察fifo的特性,适用于FPGA初学者。-This procedure is based on Xilinx' s FPGA simple code written for the ip nuclear fifo simple configuration, and Simulation observed through simulation code fifo for FPGA beg
uart_fifo
- FPGA与PC的串口通信代码,使用了FIFO作为数据的缓存。-FPGA and PC serial communication code, use the FIFO as cached data.
TransfData
- 用于FPGA发送数据,采用VHDL语言编程,采用16位fifo发送,内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal
uart
- 黑金FPGA开发板串口收发程序,其中加入FIFO模块作为输入输出缓冲-Black gold development board FPGA procedures, which joined the FIFO module as input and output buffer
USB_FPGA
- 通过FPGA控制USB实现Slave FIFO模式下的数据传输-achieve the data sending and recieving throgh FPGA by controling the USB working in the Slave FIFO mode
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
fifo_matlab
- fifo设计的matlab程序,是FPGA设计的重要参考,非常好用-fifo design