搜索资源列表
18a
- 匹配滤波器设计，VERILOG实现的，比较好的哦-Matched filter design, VERILOG implementation, and better oh
VGA_Pattern
- FPGA用于控制VGA数模转换芯片ADV7123的Verilog控制代码；实现了VGA的显示时序，输出包括vga_hs,vga_vs,vga_clk,vga_blank,vga_sync,vga_R,vga_G,vga_B-The verilog code for control ADV7123 with FPGA.
8051IP_Verilog
- 8051核，verilog实现。可以直接用在FPGA中，在此基础上可以和用真正的8051一样的进行单片机的学习。-8051 Nuclear, verilog achieve. Can be directly used in the FPGA, in this basis can be used as the real conduct of the 8051 single-chip learning.
robertvision
- 基于FPGA的嵌入式机器人视觉识别系统模块源代码，也包括了所有硬件设计资料，是VERILOG格式-Embedded FPGA-based Robot Vision Recognition System module source code, including all hardware design information
FPGA_SDRAM_PCI
- 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
crc7
- CRC计算模块，7位CRC计算。经过FPGA及IC平台验证。-CRC calculation module, 7 CRC calculation. Through the FPGA and IC platform for verification.
HDMI
- HDMI interface verilog code and specificaiton paper
router_routing
- 片上网络NOC基于fpga实现的，routing模块。-NOC-chip networks realized fpga-based, routing module.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
FPGA_examples
- FPGA工程例子.verilog HDL语言编写；-FPGA project examples. Verilog HDL language
SmallPC2
- 利用fpga设计最小系统的verilog程序。-Minimum system design using fpga verilog program.
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Verilog_ADCtestcode
- ADC测试的verilog代码，可以下载到FPGA上面实现对ADC性能测试。-the test code for ADC of verilog
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
syn_frame
- 基于verilog的帧同步搜索,fpga中可以实现帧头搜索，进而实现同步，并有一定的容错能力-verilog-based frame synchronization searching
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
FSK
- 频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证-Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board