搜索资源列表
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
DAC8812
- DA转换，Verilog HDL 编的，可实现DA转化。DA芯片用的是DAC8812，实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
video_from_opencore
- 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
vga
- 基于EPM1270的VGA显示器接口源码Verilog-Based on the EPM1270
adder
- cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
FPGAdezizhixingSPWMboChengXu
- 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
VGA
- 基于FPGA嵌入式开发实现的VGA接口，已经验证通过。-FPGA-based embedded development to achieve the VGA interface, has been adopted to verify.
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
fpgashixiantongxin
- 提出了一种利用FPGA技术解决ARINC429通信的实现方案,该方案不仅使国内的ARINC429通信设备摆脱了对国外ASIC电路的依赖,还降低了设备成本,并且克服了国外ASIC电路的不足,实现了任意长度数据帧的群收和群发功能,具有较好的应用前景。利用该方案研制的ARINC429数据通信卡,已成功应用于空空导弹测控设备中。 -A use of FPGA technology to solve ARINC429 Communication program, which not only make
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
I2C_test
- FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.-FPGA EP2C5Q288C8 I2C original code, test that is used to open OK.
VDHL
- Verilog的135个经典设计实例，直流电机控制，游戏机，三态总线，加法器，锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
multiclock_design_guide
- 在FPGA设计中，多时钟设计策略。采用verilog描述。-In the FPGA design, multi-clock design strategy. Using Verilog descr iption.
sha_core
- 安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box
butfly4
- 基4-FFT蝶形单元实现，按照FPGA内部的乘法器功能编写的-4-FFT butterfly-based unit to achieve, in accordance with the internal FPGA multiplier feature prepared