搜索资源列表
3.2_SetPLL
- 流明ARM开发板设置PLL锁相环时钟示例程序，可以直接在IAR编译器上运行使用。-Lumens ARM development board PLL set phase lock loop clock example program, can direct IAR compilers run use.
ANOlog_TMS320F28335
- 本装置采用单相桥式DC-AC逆变电路结构，以TI公司的浮点数字信号控制器TMS320F28335 DSP为控制电路核心，采用规则采样法和DSP片内ePWM模块功能实现SPWM波。最大功率点跟踪（MPPT）采用了恒压跟踪法（CVT法）来实现，并用软件锁相环进行系统的同频、同相控制，控制灵活简单。采用DSP片内12位A/D对各模拟信号进行采集检测，简化了系统设计和成本。本装置具有良好的数字显示功能，采用CPLD自行设计驱动的4.3’’彩色液晶TFT LCD非常直观地完成了输出信号波形、频谱特性的在线
PLL
- The simulation file is the Phase lock loop with dq theory with unbalance input volatges
Project_PLL
- 飞思卡尔单片机锁相环设置，基于xs128.- Freescale single-chip microcomputer and phase lock loop Settings, based on xs128.
A-novel-algorithm-implementing-PLL
- 设计了一种新颖的三相锁相环的设计算法，可以用于不平衡电压的相位检测和跟踪。-A modified soft phase lock loop algorithm improving the performance inDynamic phase tracking and detection of unbalanced voltage
eda
- EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时
PLL_1
- 为锁相回路或锁相环，用来统一整合时脉讯号，使内存能正确的存取资料。PLL用于振荡器中的反馈技术。 许多电子设备要正常工作，通常需要外部的输入信号与内部的振荡信号同步，利 用锁相环路就可以实现这个目的。-For phase lock loop or phase lock loop, the unification and the integration of the pulse signal used to when, make memory can correct access material
PLL_for_LPC2129
- Phase Lock Loop interface with ARM7TDMI. This is very useful for PLL programming.Its based on philips LPC2129 microcontroller
psk31_9b_12a
- PSK31 Model with Symbol Timing and Carrier Recovery-This model implements a communication standard known as PSK31. The transmit portion of the model can either synthesize the PSK31 signal, or use real world signals that were captured as Wave files.
Design-of-All-Digital-FM-Receiver-Circuit
- all digital phase lock loop
PLL
- LPC2114平台，验证锁相环功能，并通过proteus仿真-LPC2114 platform, validation and phase lock loop function, and through the proteus simulation
EET_2140_Module_14_s08_PLL
- This phase lock loop method the is often used to demodulate FM signals-This is phase lock loop method the is often used to demodulate FM signals
sanxiangsuoxiang
- 可实现电网相角的无静差跟踪，即实现锁相功能，可以在1到2个周期内实现锁相功能-PLL PHASE LOCK LOOP
pll
- 用c语言实现的pll锁相环。用于仿真信号锁相。-pll phase lock loop。
MATLAB-Model
- 光伏微网逆变器并网matlab/simulink仿真，仿真效果很好，mppt环节采用扰动跟踪法，锁相环部分使用s-function编译-Solar Micro Inverter Grid matlab/simulink simulation, the simulation results very well, mppt link tracking using perturbation method, phase lock loop section compiled using s-functio
05386026
- In a series of papers in recent years new structures for coherent M-PSK (M-ary Phase Shift Keying) receivers were suggested. These include structures for carrier phase detectors for the carrier PLL (Phase Lock Loop), carrier PLL lock dete
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
aaa
- 一种全数字时钟数据恢复电路的设计与实现，提出一种改进型超前滞后锁相环法的全数字时钟恢复算法，与同类电路比较，具有数据码率捕获范围宽、捕获时间短的优点。-Clock Date Recovery(CDR)circuit is a important part of data transmission equipment．For the burst data transmission，the traditional phase—lock loop can hardly achieve the re
FLL_PLL_demo
- Demo that shows how Phase Lock Loop and Frequency locked loop works.
commfreqsyn
- 锁相频率合成器的simulink模型，可验证电路设计的工作过程和合理性。-Phase lock loop