搜索资源列表
DPLL
- 全数字锁相环的verilog设计,已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
DigLockLoop
- VHDL设计的数字锁相环,可供设计参考。-digtal lock phase loop。
Filter
- 该代码主要实现环路滤波器矩阵的设计,环路滤波器的功能主要是在鉴相器的输出端衰减高频误差分量,以提高抗干扰性能;在环路跳出锁定状态时,提高环路以短期存储,并迅速恢复信号。-The code mainly realizes the design of loop filter matrix, Loop filter function is mainly in the output of the phase discriminator attenuation of high frequency erro
Phase_detection
- PLL锁相环 输入三相电压电流 输出电角度 DQ轴电压电流-Phase Loop Lock Input: 3_phase voltage¤t output: angle & DQ-axis Voltage&Current
untitledsuoxiang
- 并网锁相:用积分法实现90滞后的单相光伏并网锁相环-Grid lock-in: 90 integral method to achieve lag phase photovoltaic grid-locked loop single
suoxianghuan
- 锁相环就是锁定相位的环路。学过自动控制原理的人都知道,这是一种典型的反馈控制电路,利用外部输入的参考信号控制环路内部振荡信号的频率和相位,实现输出信号频率对输入信号频率的自动跟踪,一般用于闭环跟踪电路。-Locked loop (phase), as the name implies, is the lock phase of the loop. Principle of automatic control of the people know, this is a typical feedba
SPLL
- 较为详细地介绍了单同步坐标系软件锁相环,采用了单一的同步坐标系锁相控制结构,一般适用于电网电压平衡时的相位,频率及幅值的检测,以及用于多种控制结构中(下垂控制,PQ控制,双闭环控制)。-A more detailed descr iption of the principle of a single coordinate system PLL synchronization and setting PI controller parameters. SPLL with a single sync
频率锁定 MB1504 MO -1501 .可用 - 副本
- MSP430F5438A的MB1501程序,锁相环锁定频率输出,有液晶显示,有注释说明(5MSP430F5438A MB1501 program, phase-locked loop lock frequency output, with LCD display, with notes)
任务四 Gardner位同步算法与锁相环联合仿真
- Gardner位同步算法与锁相环的联合仿真程序.加入了时偏和频偏,能很好地锁定时偏和频偏,得到最佳采样输出。(Gardner bit synchronization algorithm and phase-locked loop joint simulation program, adding time offset and frequency offset, can well lock the bias and frequency offset, get the best sampling o
基于DSP的60kW_300kHz高频感应加热电源
- 介绍了一种基于DSP 的高频感应加热电源。现以MOSFET为开关器件,并通过逆变器并联扩容为60kW/300kHz。采用多重斩波技术,增大了斩波电路的容量,将基于DSP 的fuzzy-DPLL 复合数字锁相环技术应用在高频场合,使锁相有快速的动态性能和高精度的稳态性能,实现了对负载频率的可靠跟踪及对逆变状态的可靠控制,提高了逆变器 的工作效率和功率因数。(A high frequency induction heating power supply based on DSP. MOSFET i
dpll源程序
- 一种设计数字锁相环的思路,包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等,实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
基于DSP28335的单相PWM整流 双闭环PI控制
- 利用DSPF28335实现单相桥式PWM整流器的双闭环PI控制,用到AD7606和数字锁相(Double-closed-loop PI control of single-phase bridge PWM rectifier using DSPF28335, using AD7606 and digital phase lock)
PLL(锁相环)_TEST_OK
- 通过STM32程序的编写来形成闭环锁相环,锁住波形的稳定,保持系统的稳定。(Through the preparation of STM32 program to form a closed-loop phase-locked loop, lock waveform stability, maintain the stability of the system)