搜索资源列表
777777
- 本文件关于AES密码机的设计过程，从系统体系结构设计到RTL代码的实现-The document on AES cipher machine design process, system architecture design to implementation RTL code
RTL
- PWM controller in VHDL
PIC18F67K22-Salinity_sd-program
- 使用PIC18F67K22 单片机，编写盐度，加速度，时钟，温度，accelerated speed，SD 卡陀螺仪源代码，编译调试OKAY!-PIC18F67K22 PROGRAM FOR salinity, velocity,RTL，accelerated speed， SD CARD SOURCE CODE
spi_rtl
- 支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
parse_weights
- parse weights in neural network for use in rtl. It can be used to convert weights files generated by training to binary input for the rtl.
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
lcd1.tar
- LCD Control RTL Verilog Code
GSPI_IF
- GV7601 GSPI FPGA实现代码-GV7601 GSPI RTL
I2S_IF
- GV7601 I2S FPGA实现的功能-GV7601 I2S RTL
clk_gen
- 常见的FPGA 时钟模块代码实例，仅供大家参考-FPGA clock RTL
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
ChannelizerFFT
- FFT 模型，能够演示多通道FFT的实现过程。-FFT Multi-channel model. This simulink model can generate RTL code via Synplify DSP.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
fir filter vhdl code
- FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
pipe_mul
- 移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。-multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle
RDSigGen
- 北斗一代信号源RTL源代码，可以生产RDSS中频数字信号。-RTL source code for BD1 signal.
rtl
- amba apb3.0 的桥代码，经过验证，完全正确-amba apb3.0 bridge code, proven completely correct
ss_pcm.tar
- PCM Verilog RTL Reference Code
test_rtls
- RTl hardware generation