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memory-controller
- 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
sdram_controller
- SDRAM Controller Source Code
sdram_mdl
- verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
ug_ddr_sdram
- DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
FDDDDRSDRAMP
- 一种基于FPGA 实现DDDR SDRAM的控制器 -DDDR SDRAM controller based on FPGA
childers
- micron data sheet for designing the ddr2 sdram controller part2
eetop.cn_SDRAM
- 实现sdram控制器的verilog代码，很好的学习资料-The sdram controller verilog code, very good learning materials
sdram_controller
- 该模块是一个基于FPGA的SDRAM控制器，该模块有两个接口，一个接口是系统接口，一个连接SDRAM的接口。可以适应不同速度和带宽的SDRAM。-This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other
SDRAM_control_design
- 一个SDRAM控制器的参考设计vhdl语言，包含了全部逻辑功能代码以及约束文件，包括一些综合布线后的文件和波形，有较高的参考价值。-A SDRAM controller reference design vhdl language contains all logic code as well as the constraints file, including files and waveform integrated wiring, there is a high reference val
sdr_ctrl
- SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source descr iption
DDRSDRAM
- 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
verilog
- it is xilinx SDR SDRAM controller core
SDRAM_Source
- DE2 Board SDRAM Controller
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
DDRSDRAMverilog
- 本文介绍了sdram控制器的。本文附上了介绍文档，具有详细的说明。-This article describes the sdram controller. The attached introductory document, a detailed descr iption.
Sdram_Control_4Port
- 文档介绍了SDRAM控制器，带有四个fifo,希望对初学者有一定的帮助。-The document describes the SDRAM controller with four fifo some help for beginners.