搜索资源列表
usbvhdl
- usb 代码 用VHDL编写 方便初学者使用 学习 有什么不明白的 大家可以回复 互相交流-usb using VHDL code to facilitate the preparation of beginners to learn what we do not understand each other can return exchange
usb_vhdl
- the vhdl model of usb. it is very helpful.-vhdl model of the usb. It is very helpful.
pingpongjiegou
- VHDL编译,本程序是从USB GPIF口SRAM传输数据,且形成乒乓结构传输-VHDL compiler, the procedure is GPIF USB port SRAM transmission of data, Structure formation and transmission Table Tennis
Chapter6Sample
- Chapter6Sample,FPGA嵌入式开发书籍的源码,其中含有USB控制器的设计 VHDL语言开发-Chapter6Sample, FPGA embedded development books source code, USB controller contains the VHDL Design Development
Chapter7Sample
- Chapter6Sample,FPGA嵌入式开发书籍的源码,其中含有USB控制器的设计 VHDL语言开发-Chapter6Sample, FPGA embedded development books source code, USB controller contains the VHDL Design Development
altera_USB_blaste
- altera USB blaste 制作全套资料。包括原理图、93LC46的配置文件和CPLD的VHDL源程序。-altera USB blaste produced full set of information. Including drawings, 93LC46 configuration files and CPLD VHDL source.
USB_VHDL_CODE
- USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发,是一个不错的源码。
jtag_logic
- USB下载线的vhdl程序,实现USB协议和JTAG接口的转换,用状态机实现的
usb_xilinx_vhdl
- usb源码_xilinx_vhdl 这是Xilinx FPGA上的usb源码(VHDL)
USB_VHDL
- USB总线接口的VHDL实现,希望对大家有帮助
usb1c6
- 基于fpga和sopc的用VHDL语言编写的EDA的USB控制模块程序
la_usb-SPISRAM
- 有关到SRAM的VHDL程序,也涉及到USB接口,希望对大家有所帮助
usb_xilinx_vhdl
- 基于FPGA的usb程序,采用VHDL语言编写。
ad_convert
- 用cpld控制时序通过usb传送数据到pc机的vhdl源码,用于一款心电图机。
usb_xilinx
- usb的接口资料,vhdl
USB_Verilog_IP
- USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
lcd-code
- 比较完整的LCD接口代码,verilog编写,分为6800和8080两种CPU接口,且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
T3_USB_OUT
- cy7c68013向外部发送一个数据 ,发送至fpga,fpga的实例程序 -CY7C68013 to send an external data, sent to the fpga, fpga examples of procedures
Fifo
- 一个FIFO源代码,基于Altera FPGA-A FIFO source code, based on Altera FPGA
USBipcore
- usb1.1 ip核,使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog